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51. 发明授权

US08043920B2 finFETS and methods of making same 有权
标题翻译： finFETs及其制作方法
公开(公告)号：US08043920B2
公开(公告)日：2011-10-25
申请号：US12561606
申请日：2009-09-17
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
摘要翻译：一种合并多鳍鳍鳍鳍片的制造方法和结构。该方法包括从具有非常薄的掩埋氧化物层的SOI衬底的硅层形成单晶硅散热片，并通过从衬底生长垂直外延硅并从散热片的端部生成水平外延硅，从而将翅片的端部区域合并垂直外延硅生长占优势。

52. 发明申请

US20110193166A1 STRUCTURE AND METHOD FOR REDUCING FLOATING BODY EFFECT OF SOI MOSFETS 有权
标题翻译：降低SOI MOSFET浮体效应的结构和方法
公开(公告)号：US20110193166A1
公开(公告)日：2011-08-11
申请号：US12700797
申请日：2010-02-05
申请人： Qingqing LIANG , Huilong ZHU , Zhijiong LUO , Haizhou YIN
发明人： Qingqing LIANG , Huilong ZHU , Zhijiong LUO , Haizhou YIN
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L29/6675 , H01L29/78615 , H01L29/78624 , H01L29/78687
摘要： The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
摘要翻译：本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

53. 发明授权

US07989297B2 Asymmetric epitaxy and application thereof 有权
标题翻译：不对称外延及其应用
公开(公告)号：US07989297B2
公开(公告)日：2011-08-02
申请号：US12614699
申请日：2009-11-09
申请人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
发明人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

54. 发明申请

US20110169088A1 STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 失效
标题翻译：具有绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的半导体的非对称结或反向HALO分布的结构和方法
公开(公告)号：US20110169088A1
公开(公告)日：2011-07-14
申请号：US12686402
申请日：2010-01-13
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

55. 发明授权

US07977712B2 Asymmetric source and drain field effect structure 有权
标题翻译：不对称源极和漏极场效应结构
公开(公告)号：US07977712B2
公开(公告)日：2011-07-12
申请号：US12059059
申请日：2008-03-31
申请人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
发明人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/28132 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.
摘要翻译：诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域。

56. 发明申请

US20100203708A1 AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES 有权
标题翻译：用于混合定向衬底的拟合/调制再结晶方法
公开(公告)号：US20100203708A1
公开(公告)日：2010-08-12
申请号：US12767261
申请日：2010-04-26
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/26 , H01L21/322
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

57. 发明授权

US07704852B2 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07704852B2
公开(公告)日：2010-04-27
申请号：US11871694
申请日：2007-10-12
申请人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

58. 发明授权

US07691733B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
标题翻译：激光加工方法用于封闭几何中的无边缘无缺陷固相外延
公开(公告)号：US07691733B2
公开(公告)日：2010-04-06
申请号：US12062749
申请日：2008-04-04
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

59. 发明申请

US20090298297A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20090298297A1
公开(公告)日：2009-12-03
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

60. 发明申请

US20080185658A1 Buried Stress Isolation for High-Performance CMOS Technology 失效
标题翻译：埋地应力隔离用于高性能CMOS技术
公开(公告)号：US20080185658A1
公开(公告)日：2008-08-07
申请号：US12099195
申请日：2008-04-08
申请人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
发明人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
IPC分类号： H01L27/08 , H01L21/8238
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
摘要翻译：场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

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