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1. 发明授权

US08558282B1 Germanium lateral bipolar junction transistor 有权
公开(公告)号：US08558282B1
公开(公告)日：2013-10-15
申请号：US13607672
申请日：2012-09-08
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

2. 发明申请

US20130260526A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 有权
公开(公告)号：US20130260526A1
公开(公告)日：2013-10-03
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

3. 发明申请

US20130140634A1 METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION 有权
标题翻译：在集成电路芯片制造中用金属替代硅的方法
公开(公告)号：US20130140634A1
公开(公告)日：2013-06-06
申请号：US13310796
申请日：2011-12-05
申请人： Kevin K. Chan , Christopher D'Emic , Young-Hee Kim , Dae-gyu Park , Jeng-Bang Yau
发明人： Kevin K. Chan , Christopher D'Emic , Young-Hee Kim , Dae-gyu Park , Jeng-Bang Yau
IPC分类号： H01L29/786 , H01L21/283 , H01L21/28
CPC分类号： H01L27/088 , H01L21/76283 , H01L21/76879 , H01L21/76886 , H01L21/823437 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66772
摘要： A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
摘要翻译：用金属替代半导体材料的方法，替代金属栅场效应晶体管（RMG FET）和触点（RMC）以及包括FET和/或RMC的集成电路（IC）芯片。图案化的半导体层，例如硅，形成在电介质层，例如层状栅极电介质上。场介电层填充图案化的半导体层中的形状之间。金属沉积在形状上。将晶片退火以用金属代替每种形状的半导体，以形成金属FET栅极或触点。

4. 发明授权

US08445969B2 High pressure deuterium treatment for semiconductor/high-K insulator interface 有权
标题翻译：用于半导体/高K绝缘子接口的高压氘处理
公开(公告)号：US08445969B2
公开(公告)日：2013-05-21
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

5. 发明授权

US08421191B2 Monolayer dopant embedded stressor for advanced CMOS 有权
标题翻译：单层掺杂剂嵌入式应力器用于高级CMOS
公开(公告)号：US08421191B2
公开(公告)日：2013-04-16
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L31/117
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

6. 发明申请

US20130032883A1 FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING 有权
公开(公告)号：US20130032883A1
公开(公告)日：2013-02-07
申请号：US13198255
申请日：2011-08-04
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/24
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

7. 发明授权

US08288222B2 Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 有权
标题翻译：应用聚束束注入制造阈值电压调节FET
公开(公告)号：US08288222B2
公开(公告)日：2012-10-16
申请号：US12582139
申请日：2009-10-20
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
摘要翻译：提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从聚束束植入步骤后的结构。

8. 发明申请

US20120098067A1 STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：高K金属栅极半导体晶体管的结构
公开(公告)号：US20120098067A1
公开(公告)日：2012-04-26
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

9. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

10. 发明授权

US07911008B2 SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS 有权
标题翻译：具有用于平面通过栅极和平面下拉NFET的矩形组合有源区的SRAM单元
公开(公告)号：US07911008B2
公开(公告)日：2011-03-22
申请号：US11924059
申请日：2007-10-25
申请人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
发明人： Xiangdong Chen , Shang-Bin Ko , Dae-Gyu Park
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/11
摘要： A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
摘要翻译：平面通栅NFET被设计成具有与平面下拉NFET相同的宽度。为了优化平面下拉NFET和邻接的平面通过栅极NFET之间的β比率，通过向平面通过栅极NFET提供不同的高k金属栅极堆叠来增加平面栅极NFET的阈值电压，而不是平面下拉NFET。特别地，形成在高k电介质层上的阈值电压调节电介质层保留在平面通过栅极NFET中，并在平面下拉式NFET中去除。用于平面通过栅极NFET和平面下拉NFET的组合NFET有源区域基本上是矩形的，这使得能够通过光刻装置对组合的NFET有源区域的图像进行高保真打印。

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