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51. 发明申请

US20100020616A1 Soft Errors Handling in EEPROM Devices 有权
标题翻译： EEPROM设备中的软错误处理
公开(公告)号：US20100020616A1
公开(公告)日：2010-01-28
申请号：US12572098
申请日：2009-10-01
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C16/04
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

52. 发明授权

US07630237B2 System and method for programming cells in non-volatile integrated memory devices 有权
标题翻译：用于在非易失性集成存储器件中编程单元的系统和方法
公开(公告)号：US07630237B2
公开(公告)日：2009-12-08
申请号：US11196547
申请日：2005-08-02
申请人： Nima Mokhlesi , Daniel C. Guterman
发明人： Nima Mokhlesi , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5671 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C2211/5621
摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.
摘要翻译：提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

53. 发明申请

US20090268518A1 Novel Multi-State Memory 有权
标题翻译：新型多态内存
公开(公告)号：US20090268518A1
公开(公告)日：2009-10-29
申请号：US12499581
申请日：2009-07-08
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

54. 发明授权

US07548461B2 Soft errors handling in EEPROM devices 失效
公开(公告)号：US07548461B2
公开(公告)日：2009-06-16
申请号：US10874825
申请日：2004-06-22
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C11/34
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

55. 发明授权

US07443726B2 Systems for alternate row-based reading and writing for non-volatile memory 有权
标题翻译：用于非易失性存储器的替代行读和写的系统
公开(公告)号：US07443726B2
公开(公告)日：2008-10-28
申请号：US11321346
申请日：2005-12-29
申请人： Daniel C. Guterman
发明人： Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5622
摘要： A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.
摘要翻译：一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。然后编程WLn + 1。根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...，。。 }直到所有集合的最后一个字线都被编程为止。然后编程最后一个字线。通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。在不使用基于相邻存储单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

56. 发明授权

US07397698B2 Reducing floating gate to floating gate coupling effect 有权
标题翻译：降低浮栅耦合效应
公开(公告)号：US07397698B2
公开(公告)日：2008-07-08
申请号：US11735265
申请日：2007-04-13
申请人： Yupin Fong , Daniel C. Guterman
发明人： Yupin Fong , Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/16
摘要： For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.
摘要翻译：对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效数据阈值电压窗口。降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

57. 发明申请

US20080130364A1 Novel Multi-State Memory 审中-公开
公开(公告)号：US20080130364A1
公开(公告)日：2008-06-05
申请号：US12016045
申请日：2008-01-17
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

58. 发明授权

US07360136B2 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data 有权
标题翻译：通过使用有关存储数据质量的信息，提高纠错码的有效性和操作多级存储器系统
公开(公告)号：US07360136B2
公开(公告)日：2008-04-15
申请号：US10866554
申请日：2004-06-10
申请人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C16/3418 , G06F11/1012 , G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/3431 , G11C29/00 , G11C29/42 , G11C29/76 , G11C2029/0411
摘要： The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the qualify indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.
摘要翻译：通过不同的方法评估存储在存储器系统中的数据的质量，并且根据评估的质量操作存储器系统。在读取操作期间可以评估数据质量。随后使用纠错码可以利用质量指示来提高检测和重建数据的效率。或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于资格指示提供的知识，可以提高效率。这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。

59. 发明授权

US07345934B2 Multi-state memory 有权
标题翻译：多状态存储器
公开(公告)号：US07345934B2
公开(公告)日：2008-03-18
申请号：US11105855
申请日：2005-04-14
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C7/00
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

60. 发明授权

US07342279B2 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US07342279B2
公开(公告)日：2008-03-11
申请号：US11075423
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
发明人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

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