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51. 发明授权

US09564326B2 Lithography using interface reaction 有权
标题翻译：光刻使用界面反应
公开(公告)号：US09564326B2
公开(公告)日：2017-02-07
申请号：US14333544
申请日：2014-07-17
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/033 , H01L21/268 , H01L21/308 , H01L21/311 , H01L29/78 , H01L21/027 , H01L21/3105 , H01L21/324
CPC分类号： H01L21/0337 , H01L21/0274 , H01L21/0332 , H01L21/31055 , H01L21/31144 , H01L21/324
摘要： A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties and the third mask is a combination of the first mask and the second mask.
摘要翻译：一种形成半导体结构的方法，在第一掩模中形成第一掩模沟槽，其中第一掩模在衬底上; 在第一掩模沟槽中形成第二掩模; 以及通过使所述第一掩模与所述第二掩模反应而在所述第一掩模和所述第二掩模之间形成第三掩模，其中所述第一掩模，所述第二掩模和所述第三掩模都具有不同的蚀刻性质，并且所述第三掩模是所述第一掩模第一个面具和第二个面具。

52. 发明授权

US09559009B2 Gate structure cut after formation of epitaxial active regions 有权
标题翻译：形成外延活性区后的门结构切割
公开(公告)号：US09559009B2
公开(公告)日：2017-01-31
申请号：US14876212
申请日：2015-10-06
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc.
发明人： Xiuyu Cai , Kangguo Cheng , Johnathan E. Faltermeier , Ali Khakifirooz , Theodorus E. Standaert , Ruilong Xie
IPC分类号： H01L21/311 , H01L21/8234 , H01L29/417 , H01L27/088 , H01L29/08 , H01L21/84 , H01L29/66
CPC分类号： H01L21/823437 , H01L21/31111 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/66795 , H01L29/785
摘要： A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.
摘要翻译：形成跨越多个半导体材料部分的栅极结构。源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。通过选择性外延工艺从源极和漏极区域形成外延有源区。通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

53. 发明申请

US20170005088A1 DISTRIBUTED DECOUPLING CAPACITOR 审中-公开
标题翻译：分布式解耦电容器
公开(公告)号：US20170005088A1
公开(公告)日：2017-01-05
申请号：US15235775
申请日：2016-08-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Ali Khakifirooz , Darsen D. Lu , Ghavam G. Shahidi
IPC分类号： H01L27/06 , H01L23/528 , H01L49/02 , H01L21/8234 , H01L23/522
摘要： An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
摘要翻译：一种包括多个翅片结构的电气装置。多个翅片结构包括至少一个去耦翅片和至少一个半导体翅片。电气装置包括至少一个半导体器件，其包括存在于至少一个半导体鳍片中的沟道区域，存在于至少一个半导体鳍片的沟道区域上的栅极结构以及存在于源极和漏极区域部分上的源极和漏极区域的至少一个半导体鳍片。电气装置包括至少一个去耦电容器，其包括作为去耦电容器的第一电极的去耦鳍结构，节点电介质层和由金属接触件提供到半导体鳍片结构的源极和漏极区域的第二电极。去耦电容器位于电力线下方到半导体鳍结构。

54. 发明授权

US09536877B2 Methods of forming different spacer structures on integrated circuit products having differing gate pitch dimensions and the resulting products 有权
标题翻译：在具有不同栅间距尺寸的集成电路产品上形成不同间隔结构的方法以及所得产品
公开(公告)号：US09536877B2
公开(公告)日：2017-01-03
申请号：US14195484
申请日：2014-03-03
申请人： GLOBALFOUNDRIES Inc. , International Business Machines Corporation
发明人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L27/088 , H01L23/485 , H01L21/768 , H01L23/532
CPC分类号： H01L27/088 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.
摘要翻译：本文公开的一个示例涉及将源极/漏极导电触点形成到第一和第二源极/漏极区域，第一源极/漏极区域位于具有第一栅极间距尺寸的第一对晶体管器件之间，第二源极/漏极区域被定位在具有大于第一栅极间距尺寸的第二栅极间距尺寸的第二对晶体管器件之间，其中第一和第二对晶体管器件具有栅极结构和邻近栅极结构定位的侧壁间隔物。

55. 发明申请

US20160380074A1 METHOD OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH ABRUPT JUNCTIONS AND INTEGRATED CIRCUIT CHIPS WITH THE FETS 有权
标题翻译：用场效应晶体管形成场效应晶体管（FET）的方法和集成电路芯片
公开(公告)号：US20160380074A1
公开(公告)日：2016-12-29
申请号：US14750120
申请日：2015-06-25
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/66 , H01L29/06 , H01L21/283 , H01L21/321 , H01L21/3213 , H01L29/49 , H01L27/088 , H01L21/225
CPC分类号： H01L21/823828 , H01L21/2251 , H01L21/2254 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/0649 , H01L29/495 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel.
摘要翻译：一种用FET形成场效应晶体管（FET）和集成电路（IC）芯片的方法。在场效应晶体管的每个通道的通道占位符都被削弱。与每个通道占位符相邻的源极/漏极区域延伸到并填充底切。打开通道占位符，以暴露每个通道占位符下的通道表面。在每个通道占位符下形成源极/漏极延伸部分，与每个源极/漏极区域相邻。在移除通道占位符之后，在每个所述FET通道上形成金属栅极。

56. 发明申请

US20160379894A1 Semiconductor Device Structure With 110-PFET and 111-NFET Current Flow Direction 有权
标题翻译：具有110-PFET和111-NFET电流流动方向的半导体器件结构
公开(公告)号：US20160379894A1
公开(公告)日：2016-12-29
申请号：US15246963
申请日：2016-08-25
申请人： International Business Machines Corporation
发明人： Pouya Hashemi , Ali Khakifirooz , Shogo Mochizuki , Alexander Reznicek
IPC分类号： H01L21/84 , H01L21/306 , H01L21/762 , H01L21/02 , H01L29/04 , H01L27/12
CPC分类号： H01L27/1211 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/30604 , H01L21/30608 , H01L21/76251 , H01L21/76286 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1207 , H01L29/045 , H01L29/0649 , H01L29/0673 , H01L29/161 , H01L29/167
摘要： A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
摘要翻译： FinFET包括具有（100）硅的顶部晶片，（110）硅的处理晶片和在顶部晶片和处理晶片之间的掩埋氧化物层的混合衬底; 设置在所述顶部晶片中并沿（100）硅的<110>方向定向的第一组翅片; 以及设置在所述手柄晶片中并沿（110）硅的<112>方向取向的第二组翅片。第一组翅片和第二组翼片对齐。

57. 发明申请

US20160351689A1 SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE 审中-公开
标题翻译：具有L形底板的半导体结构
公开(公告)号：US20160351689A1
公开(公告)日：2016-12-01
申请号：US15212311
申请日：2016-07-18
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Davood Shahrjerdi
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/66666 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823487 , H01L21/84 , H01L27/088 , H01L29/0649 , H01L29/0847 , H01L29/1037 , H01L29/41741 , H01L29/42392 , H01L29/66484 , H01L29/66545 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.
摘要翻译：提供一种形成半导体结构的方法。该方法包括在源极/漏极材料的第一层上相对于第一垂直沟道垂直地形成第一垂直沟道，以及通过去除源/漏的第一层的一个或多个部分来形成第一源极/漏极半导体结构材料，使得i）第一源极/漏极半导体结构具有与第一垂直沟道的垂直侧基本上平面的垂直侧，以及ii）源极/漏极的宽度大于第一垂直沟道的宽度，其中所述第一源极/漏极半导体结构从其垂直方向垂直地延伸，所述第一源极/漏极半导体结构比所述第一垂直沟道垂直地从其垂直侧垂直延伸。

58. 发明授权

US09508741B2 CMOS structure on SSOI wafer 有权
标题翻译： SSOI晶圆上的CMOS结构
公开(公告)号：US09508741B2
公开(公告)日：2016-11-29
申请号：US14618397
申请日：2015-02-10
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Hong He , Ali Khakifirooz , Junli Wang
IPC分类号： H01L23/48 , H01L27/12 , H01L21/84 , H01L21/8238 , H01L29/78 , H01L21/02 , H01L21/306 , H01L21/027 , H01L27/092
CPC分类号： H01L27/1207 , H01L21/02532 , H01L21/0276 , H01L21/30604 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7849
摘要： A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.
摘要翻译：描述了在包括p型场效应晶体管器件（pFET）和n型场效应晶体管（nFET）器件和CMOS器件的互补金属氧化物半导体（CMOS）器件中形成鳍的方法。该方法包括在pFET区域和nFET区域中形成应变绝缘体上硅（silicon-on-insulator，SSOI）层，仅在pFET区域中蚀刻应变硅层，绝缘体和一部分本体衬底以暴露体衬底，仅在pFET区域中从体衬底外延生长硅（Si），并且在仅在pFET区域中在Si上外延生长另外的半导体材料。该方法还包括从附加半导体材料形成散热片和在pFET区域中在体衬底上生长的Si的一部分，以及从nFET区域中的应变硅层和绝缘体形成翅片。

59. 发明申请

US20160336428A1 LOCAL SOI FINS WITH MULTIPLE HEIGHTS 有权
标题翻译：具有多个高度的本地SOI FINS
公开(公告)号：US20160336428A1
公开(公告)日：2016-11-17
申请号：US14712516
申请日：2015-05-14
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Joel P. de Souza , Ali Khakifirooz , Alexander Reznicek , Dominic J. Schepis
IPC分类号： H01L29/66 , H01L21/225 , H01L29/167 , H01L29/06 , H01L29/78
CPC分类号： H01L27/1211 , H01L21/2251 , H01L21/76243 , H01L21/823431 , H01L21/845 , H01L29/0642 , H01L29/167 , H01L29/36 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin.
摘要翻译：提供了包含具有不同高度的硅散热片的半导体结构，同时为了工艺可行性而保持合理的翅片高宽比。半导体结构包括第一高度的第一硅片，并位于第一氧化物结构的基座部分上。该结构还包括第二高度的第二硅片，并位于第二氧化物结构的基座部分上。第一氧化物结构和第二氧化物结构相互连接，第二氧化物结构具有位于第一氧化物结构的最下表面下方的最下表面。此外，第二硅片的第二高度大于第一硅片的第一高度，但是第一硅片的最顶表面与第二硅片的最顶表面共面。

60. 发明申请

US20160336235A1 DUAL WORK FUNCTION INTEGRATION FOR STACKED FINFET 有权
标题翻译：堆叠FINFET的双功能功能集成
公开(公告)号：US20160336235A1
公开(公告)日：2016-11-17
申请号：US15149360
申请日：2016-05-09
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L29/66
CPC分类号： H01L21/823821 , H01L21/8221 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L27/0688 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/78654 , H01L29/78684 , H01L29/78696 , H03K19/0948
摘要： A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a fist work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.
摘要翻译：提供了具有双功能金属栅极结构的三维叠层鳍互补金属氧化物半导体（CMOS）器件。堆叠翅片CMOS器件包括鳍片堆叠，其具有在衬底上的第一半导体鳍片，在第一半导体鳍片顶上的介电鳍片和位于介质鳍片顶部的第二半导体鳍片，以及横跨鳍片叠层的栅极袋。栅极堆叠包括围绕第一半导体鳍片的沟道部分的第一金属栅极部分和围绕第二半导体鳍片的沟道部分的第二金属栅极部分。第一金属栅极部分具有适于降低第一导电类型的场效应晶体管（FET）的阈值电压的第一功函数，而第二栅极部分具有适于降低FET的阈值电压的第二功函数与第一导电类型相反的第二导电类型。

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