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1. 发明授权

US09853116B2 Partial sacrificial dummy gate with CMOS device with high-k metal gate 有权
公开(公告)号：US09853116B2
公开(公告)日：2017-12-26
申请号：US14968471
申请日：2015-12-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dechao Guo , Wilfried E. Haensch , Shu-jen Han , Daniel J. Jaeger , Yu Lu , Keith Kwong Hon Wong
IPC分类号： H01L29/76 , H01L29/94 , H01L29/49 , H01L29/66 , H01L29/423 , H01L29/45 , H01L21/28 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28052 , H01L29/42372 , H01L29/456 , H01L29/66477 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

2. 发明申请

US20160307892A1 SEMICONDUCTOR STRUCTURE WITH AN L-SHAPED BOTTOM PLATE 有权
标题翻译：具有L形底板的半导体结构
公开(公告)号：US20160307892A1
公开(公告)日：2016-10-20
申请号：US15190543
申请日：2016-06-23
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Davood Shahrjerdi
IPC分类号： H01L27/088 , H01L29/417 , H01L29/10 , H01L29/78 , H01L29/08
CPC分类号： H01L29/66666 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823487 , H01L21/84 , H01L27/088 , H01L29/0649 , H01L29/0847 , H01L29/1037 , H01L29/41741 , H01L29/42392 , H01L29/66484 , H01L29/66545 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.
摘要翻译：具有共享共用源/漏半导体结构的相邻晶体管的半导体结构。所述相邻晶体管中的至少一个包括：垂直沟道和连接到所述垂直沟道的源极/漏极半导体结构，使得所述源极/漏极半导体结构具有与所述第一垂直沟道的垂直侧基本上平面的垂直侧。源极/漏极半导体结构从其垂直侧水平延伸，比第一垂直沟道从其垂直侧延伸，使得源极/漏极的宽度大于第一垂直沟道的宽度。第一源极/漏极半导体结构位于衬底层上，垂直沟道相对于衬底层垂直。

3. 发明申请

US20160149054A1 VERTICAL FIELD EFFECT TRANSISTORS WITH CONTROLLED OVERLAP BETWEEN GATE ELECTRODE AND SOURCE/DRAIN CONTACTS 有权
标题翻译：栅极电极与源极/漏极接触点之间具有控制叠加的垂直场效应晶体管
公开(公告)号：US20160149054A1
公开(公告)日：2016-05-26
申请号：US14938904
申请日：2015-11-12
申请人： International Business Machines Corporation
发明人： Anirban Basu , Cheng-Wei Cheng , Wilfried E. Haensch , Amlan Majumdar , Kuen-Ting Shiu
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/152 , H01L29/42392 , H01L29/66742 , H01L29/66977 , H01L29/7391 , H01L29/78642
摘要： An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
摘要翻译：形成具有受控栅极重叠的垂直场效应晶体管的半导体结构的方法。该方法包括在半导体衬底上形成第一半导体层，第二半导体层，第三半导体层，第四半导体层，第五半导体层和第一电介质层。蚀刻的第一介电层和第一漏极接触被第一间隔物包围。第一漏极接触由第五半导体层构成。形成由第四半导体层，由第三半导体层构成的沟道和由第二半导体层构成的第二源极触点构成的第二漏极接触。此外，形成由第一半导体构成的第一源极接触，并且在围绕第一柱和第二柱的一部分的第一源极接触层的一部分上形成栅电极。

4. 发明申请

US20150270187A1 FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES 有权
公开(公告)号：US20150270187A1
公开(公告)日：2015-09-24
申请号：US14732689
申请日：2015-06-06
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Wilfried E. Haensch , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L23/14 , H01L27/092 , H01L23/538 , H01L27/12
CPC分类号： H01L23/14 , H01L21/4846 , H01L21/7624 , H01L23/5381 , H01L23/5386 , H01L23/5387 , H01L27/092 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

5. 发明申请

US20150221884A1 CARBON NANOTUBE TRANSISTOR HAVING EXTENDED CONTACTS 有权
标题翻译：具有扩展联系的碳纳米管晶体管
公开(公告)号：US20150221884A1
公开(公告)日：2015-08-06
申请号：US14169340
申请日：2014-01-31
申请人： International Business Machines Corporation
发明人： Shu-Jen Han , Wilfried E. Haensch , James B. Hannon
IPC分类号： H01L51/05 , H01L51/00
CPC分类号： H01L51/0545 , B82Y10/00 , H01L51/0002 , H01L51/0048 , H01L51/0558
摘要： A semiconductor device includes a substrate that extends along a first direction to define a length and second direction perpendicular to the first direction to define a height. The substrate includes a dielectric layer and at least one gate stack formed on the dielectric layer. A source contact is formed adjacent to a first side of the gate stack and a drain contact formed adjacent to an opposing second side of the gate stack. A carbon nanotube is formed on the source contact and the drain contact. A first portion of the nanotube forms a source. A second portion forms a drain. A third portion is interposed between the source and drain to define a gate channel that extends along the first direction. The source and the drain extend along the second direction and have a greater length than the gate channel.
摘要翻译：半导体器件包括沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定高度的衬底。衬底包括介电层和形成在电介质层上的至少一个栅叠层。源极触点形成为邻近栅极堆叠的第一侧，并且与栅极堆叠的相对的第二侧相邻地形成漏极接触。在源极触点和漏极触点上形成碳纳米管。纳米管的第一部分形成源。第二部分形成排水管。第三部分介于源极和漏极之间以限定沿着第一方向延伸的栅极沟道。源极和漏极沿着第二方向延伸并且具有比栅极通道更大的长度。

6. 发明申请

US20140367786A1 FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES 有权
标题翻译：柔性，可拉伸的电子设备
公开(公告)号：US20140367786A1
公开(公告)日：2014-12-18
申请号：US13917302
申请日：2013-06-13
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Wilfried E. Haensch , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L23/14 , H01L21/4846 , H01L21/7624 , H01L23/5381 , H01L23/5386 , H01L23/5387 , H01L27/092 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.
摘要翻译：公开了制造方法，其有助于电子结构的制造，所述电子结构既柔软又可拉伸，以符合非平面（例如弯曲）表面，而不会由于过度应变而遭受功能损伤。提供包括CMOS器件的电子结构，其可以在可接受的限度内被拉伸或挤压，而不会发生故障或断裂。本文所公开的方法进一步促进了具有多级芯片内连接器的柔性可拉伸电子结构的制造。这种连接器通过沉积和光刻图案（线处理的后端）形成，并且可以在将电子结构转移到柔性基板之后被释放。

7. 发明授权

US08841716B2 Retrograde substrate for deep trench capacitors 有权
标题翻译：深沟槽电容器逆行衬底
公开(公告)号：US08841716B2
公开(公告)日：2014-09-23
申请号：US13936679
申请日：2013-07-08
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Wilfried E. Haensch , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/00 , H01L27/108 , H01L31/112 , H01L27/12 , H01L49/02 , H01L27/02 , H01L29/94 , H01L29/66 , H01L21/84 , H01L27/06
CPC分类号： H01L27/0629 , H01L21/84 , H01L21/845 , H01L27/0248 , H01L27/0255 , H01L27/10826 , H01L27/1087 , H01L27/10879 , H01L27/10894 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L31/112
摘要： A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.
摘要翻译：半导体器件包括具有第一深度的第一掺杂部分和低于第一深度的第二掺杂部分的衬底。深沟槽电容器形成在衬底中并在第一深度之下延伸。深沟槽电容器具有掩埋板，该掩埋板包括与衬底的第二掺杂部分形成导电连接并与第一掺杂部分电绝缘的掺杂剂类型。

8. 发明申请

US20140217481A1 PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE 有权
标题翻译：具有高K金属栅的CMOS器件的部分真正的门
公开(公告)号：US20140217481A1
公开(公告)日：2014-08-07
申请号：US13757809
申请日：2013-02-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dechao Guo , Wilfried E. Haensch , Shu-jen Han , Daniel J. Jaeger , Yu Lu , Keith Kwong Hon Wong
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28052 , H01L29/42372 , H01L29/456 , H01L29/66477 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.
摘要翻译：半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠：顶部上的底部，顶部和牺牲帽层; 门间隔; 源和漏区; 在除去牺牲帽层之后，在栅极堆叠的顶部和侧壁上的氮化物封装; 在氮化物封装之上的有机平面化层，平坦化封装; 并且在除去氮化物封装，有机平坦化层和栅极堆叠的顶部之后在源极和漏极区域和底部部分上进行硅化。

9. 发明申请

US20140008758A1 COMPLEMENTARY BIPOLAR INVERTER 有权
标题翻译：补充双极反相器
公开(公告)号：US20140008758A1
公开(公告)日：2014-01-09
申请号：US13949219
申请日：2013-07-23
申请人： International Business Machines Corporation
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/12 , H01L21/8228
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

10. 发明申请

US20130288447A1 VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：垂直多晶硅锗绝缘双极晶体管
公开(公告)号：US20130288447A1
公开(公告)日：2013-10-31
申请号：US13923906
申请日：2013-06-21
申请人： International Business Machines Corporation
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/737
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
摘要翻译：垂直异质结双极晶体管（HBT）包括具有掺杂第一导电类型的掺杂多晶硅作为具有约1.12eV的能带隙的宽间隙发射极，并且具有掺杂第二导电类型的掺杂单晶Ge作为基极具有约0.66eV的能量带隙。采用具有第一导电类型掺杂的掺杂单晶Ge作为集电体。因为基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。此外，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

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