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51. 发明授权

US10320496B2 Periodic calibration for communication channels by drift tracking 有权
公开(公告)号：US10320496B2
公开(公告)日：2019-06-11
申请号：US15490627
申请日：2017-04-18
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B17/11 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00 , H04B17/21 , H04B17/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

52. 发明授权

US10192609B2 Memory component with pattern register circuitry to provide data patterns for calibration 有权
公开(公告)号：US10192609B2
公开(公告)日：2019-01-29
申请号：US15633677
申请日：2017-06-26
申请人： Rambus Inc.
发明人： Craig E. Hampel , Richard E. Perego , Stefanos Sidiropoulos , Ely K. Tsern , Frederick A. Ware
IPC分类号： G11C11/4076 , G11C7/10 , G11C7/22 , G11C11/4078 , G06F12/02 , G11C11/406 , G11C21/00 , G06F3/06 , G11C11/4072 , G11C11/4093 , H04L7/00
摘要： A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

53. 发明授权

US09741424B2 Memory controller 有权
公开(公告)号：US09741424B2
公开(公告)日：2017-08-22
申请号：US15271148
申请日：2016-09-20
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00 , G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G06F1/06 , G06F1/12 , G06F3/06 , G11C7/04
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

54. 发明授权

US09667406B2 Communication channel calibration for drift conditions 有权
公开(公告)号：US09667406B2
公开(公告)日：2017-05-30
申请号：US14695597
申请日：2015-04-24
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00 , H04L7/10 , H04L25/02 , H04L25/12 , G11C7/04 , H04L7/033
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

55. 发明授权

US09628257B2 Communication channel calibration for drift conditions 有权
公开(公告)号：US09628257B2
公开(公告)日：2017-04-18
申请号：US14932192
申请日：2015-11-04
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00 , H04L7/10 , H04L25/02 , H04L25/12 , G11C7/04 , H04L7/033
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

56. 发明申请

US20160351234A1 Integrated circute with multiple request ports and link calibration support 有权
标题翻译：具有多个请求端口和链路校准支持的集成循环
公开(公告)号：US20160351234A1
公开(公告)日：2016-12-01
申请号：US15169331
申请日：2016-05-31
申请人： Rambus Inc.
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with multiple command/address ports and a memory device having corresponding request ports. The memory controller issues commands to memory device to cause the memory device to “loop-back” signals conveyed to memory device over one of the command/address ports via a bidirectional data link; these signals can be deterministic test patterns. The memory controller compares the returned information with the originally transmitted patterns to perform calibration. In one embodiment, because the return links are already calibrated, errors can be attributed to issues in the forward links; the memory controller then adjusts timing of the forward links to minimize the errors.
摘要翻译：存储器系统包括具有多个命令/地址端口的存储器控制器和具有相应请求端口的存储器件。存储器控制器向存储器件发出命令以使存储器件通过双向数据链路“循环”传送到存储器件之一的命令/地址端口之一的信号; 这些信号可以是确定性的测试模式。存储器控制器将返回的信息与原始传输的模式进行比较以执行校准。在一个实施例中，由于返回链路已被校准，错误可归因于前向链路中的问题; 存储器控制器然后调整前向链路的定时以使误差最小化。

57. 发明授权

US09472262B2 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US09472262B2
公开(公告)日：2016-10-18
申请号：US15070376
申请日：2016-03-15
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C8/00 , G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G11C7/04
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
摘要翻译：存储器控制器组件包括发射电路和调整电路。发送电路使用定时信号发送时钟信号并将数据写入DRAM，由DRAM采样的写入数据。调整电路调整写入数据和定时信号的发送定时，使得定时信号的边沿转换与DRAM处的时钟信号的边沿转换对齐。

58. 发明授权

US09378787B2 Memory controllers, systems, and methods supporting multiple request modes 有权
标题翻译：支持多种请求模式的内存控制器，系统和方法
公开(公告)号：US09378787B2
公开(公告)日：2016-06-28
申请号：US14305799
申请日：2014-06-16
申请人： Rambus Inc.
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F13/16 , G11C7/10 , G11C5/06
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

59. 发明授权

US09311976B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US09311976B2
公开(公告)日：2016-04-12
申请号：US14523922
申请日：2014-10-26
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G06F1/10 , G11C11/4076 , G11C11/409 , G11C7/04
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.
摘要翻译：具有集成电路（IC）组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储模块。选通信号路径和数据信号路径耦合到相应的IC组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有IC组件。地址/控制信号路径沿着IC组件延伸到终端结构，使得朝向终端结构传播的控制信号在对应于IC组件的相对位置的逐渐更新的时间到达各个IC组件的地址/控制输入。

60. 发明申请

US20150256325A1 Periodic Calibration For Communication Channels By Drift Tracking 有权
标题翻译：通过漂移跟踪进行通信通道的定期校准
公开(公告)号：US20150256325A1
公开(公告)日：2015-09-10
申请号：US14718019
申请日：2015-05-20
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04L7/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

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