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1. 发明申请

US20190253157A1 FREQUENCY DETECTOR FOR CLOCK RECOVERY 审中-公开
公开(公告)号：US20190253157A1
公开(公告)日：2019-08-15
申请号：US16385207
申请日：2019-04-16
申请人： PHOTONIC TECHNOLOGIES (SHANGHAI) CO., LTD.
发明人： Rui Bai , Xuefeng Chen , Wenzong Pan , Xin Wang , Tao Xia , Shang Hu , Zhichun Wang , Yuanxi Zhang , Wenjun He , Juncheng Wang , Patrick Yin Chiang
IPC分类号： H04B14/02 , H04B10/25 , H04B10/548 , H03L7/08 , H04L7/02 , H04L25/49
CPC分类号： H04L7/02 , G06F1/06 , G06F1/12 , H03K19/20 , H03K19/21 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/099 , H04B10/25 , H04B10/548 , H04B14/026 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/4902
摘要： An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

2. 发明申请

US20190212767A1 APPARATUSES FOR REDUCING CLOCK PATH POWER CONSUMPTION IN LOW POWER DYNAMIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：US20190212767A1
公开(公告)日：2019-07-11
申请号：US16357652
申请日：2019-03-19
申请人： MICRON TECHNOLOGY, INC.
发明人： Yuan He
IPC分类号： G06F1/06 , G06F1/3234 , G11C11/4076 , G11C7/22
CPC分类号： G06F1/06 , G06F1/3275 , G11C7/222 , G11C11/4076 , Y02D10/13 , Y02D10/14
摘要： Apparatus and methods of reducing dock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part, on the memory command.

3. 发明申请

US20190165925A1 PHYSICAL LAYER CIRCUITRY FOR MULTI-WIRE INTERFACE 审中-公开
公开(公告)号：US20190165925A1
公开(公告)日：2019-05-30
申请号：US16262861
申请日：2019-01-30
申请人： M31 Technology Corporation
发明人： Ching-Hsiang Chang , Yuan-Hsun Chang , Yueh-Chuan Lu , Huai-Te Wang
IPC分类号： H04L7/00 , H03K3/037 , G04F10/00 , H03F3/45 , G06F1/06 , H03K19/21 , H03K5/156 , H03K7/08 , H03K5/14
CPC分类号： H04L7/0016 , G04F10/005 , G06F1/06 , G09G3/20 , G09G5/003 , G09G2370/08 , H03F3/45475 , H03F2200/129 , H03F2203/45116 , H03F2203/45594 , H03K3/037 , H03K5/14 , H03K5/1565 , H03K7/08 , H03K19/21 , H03M7/00 , H04B1/00 , H04B1/40 , H04B1/581 , H04B3/00 , H04L25/0272 , H04L25/0292 , H04L25/0298 , H04M1/38
摘要： A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

4. 发明申请

US20190097626A1 REDUCED-POWER ELECTRONIC CIRCUITS WITH WIDE-BAND ENERGY RECOVERY USING NON-INTERFERING TOPOLOGIES 审中-公开
公开(公告)号：US20190097626A1
公开(公告)日：2019-03-28
申请号：US15974240
申请日：2018-05-08
申请人： REZONENT CORPORATION
发明人： IGNATIUS BEZZAM
IPC分类号： H03K17/687
CPC分类号： H03K3/012 , G06F1/06 , G06F1/10 , H03K3/356104 , H03K17/6872 , H03K2217/009
摘要： Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.

5. 发明申请

US20190004895A1 MEMORY SYSTEM AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20190004895A1
公开(公告)日：2019-01-03
申请号：US15879512
申请日：2018-01-25
申请人： SK hynix Inc.
发明人： Jun-Seo LEE
IPC分类号： G06F11/10 , G11C14/00 , G11C13/00 , G06F12/02 , G06F3/06
CPC分类号： G06F11/1044 , G06F1/06 , G06F3/064 , G06F3/0679 , G06F11/1048 , G06F11/108 , G06F12/0246 , G06F2212/2022 , G06F2212/7209 , G11C11/005 , G11C13/004 , G11C13/0069 , G11C14/0045 , G11C16/0483 , H03M13/1515 , H03M13/152 , H03M13/255 , H03M13/258
摘要： The memory system includes a memory device including a volatile storage area and a non-volatile storage area; and a controller including first and second interfaces for transferring data between the memory system and a host, and suitable for transferring data between the volatile storage area and the host through the first interface and transferring data between the non-volatile storage area and the host through the second interface, wherein the controller is further suitable for determining whether or not an error occurs in data read from the volatile storage area in a normal operation mode, and dumping a whole of the volatile storage area into a predetermined first location of the non-volatile storage area when an error is determined to occur in the data read from the volatile storage area.

6. 发明申请

US20180323952A1 PHYSICAL LAYER CIRCUITRY FOR MULTI-WIRE INTERFACE 审中-公开
公开(公告)号：US20180323952A1
公开(公告)日：2018-11-08
申请号：US16039348
申请日：2018-07-19
申请人： M31 Technology Corporation
发明人： Ching-Hsiang Chang , Yuan-Hsun Chang , Yueh-Chuan Lu , Huai-Te Wang
IPC分类号： H04L7/00 , H03K19/21 , H03K3/037 , H03K7/08 , G04F10/00 , H03K5/14 , H03F3/45 , G06F1/06
CPC分类号： H04L7/0016 , G04F10/005 , G06F1/06 , H03F3/45475 , H03F2200/129 , H03F2203/45116 , H03F2203/45594 , H03K3/037 , H03K5/14 , H03K5/1565 , H03K7/08 , H03K19/21 , H03M7/00 , H04B1/00 , H04B1/40 , H04B1/581 , H04B3/00 , H04M1/38
摘要： The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

7. 发明授权

US10037048B1 Methods for optimizing circuit performance via configurable clock skews 有权
公开(公告)号：US10037048B1
公开(公告)日：2018-07-31
申请号：US15464067
申请日：2017-03-20
申请人： ALTERA CORPORATION
发明人： Mark Bourgeault
IPC分类号： H03K19/00 , G06F1/10 , G06F1/06 , H03L7/07 , G06F17/50
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F17/5077 , H03K3/0375 , H03K19/1733 , H03L7/07
摘要： An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

8. 发明申请

US20180212796A1 CIRCUIT DEVICE, ELECTRONIC DEVICE, AND CABLE HARNESS 审中-公开
公开(公告)号：US20180212796A1
公开(公告)日：2018-07-26
申请号：US15876973
申请日：2018-01-22
申请人： SEIKO EPSON CORPORATION
发明人： Yoshiyuki KAMIHARA , Ryuichi KAGAYA , Toshimichi YAMADA
IPC分类号： H04L12/40 , G06F1/06 , H03L7/16 , G01R31/00 , G01R31/04 , H04L12/64
CPC分类号： H04L12/40078 , G01R31/007 , G01R31/041 , G06F1/06 , G06F11/00 , G06F13/4022 , H03L7/16 , H04L12/64
摘要： A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.

9. 发明申请

US20180188768A1 APPARATUS WITH INTER-COMMUNICATING PROCESSORS 审中-公开
公开(公告)号：US20180188768A1
公开(公告)日：2018-07-05
申请号：US15840565
申请日：2017-12-13
申请人： GN Audio A/S
发明人： Erling SKJOLDBORG
IPC分类号： G06F1/06 , H04R3/00 , G06F13/362
CPC分类号： G06F1/06 , G06F13/362 , G06F13/4269 , G06F13/4273 , H04R3/00 , H04R2420/07
摘要： The invention concerns an apparatus comprising multiple processors, such as microprocessors, that communicate with each other. The claimed apparatus provides communication between two or more processors, such as microprocessors, and enables efficient half-duplex two-way communication between two processors, each having only two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication.The apparatus (109) comprises a first processor (101) and a second processor (102), each having a first logic output pin (11, 21), a second logic output pin (12, 22), a first logic input pin (13, 23) and a second logic input pin (14, 24). For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102).Each of the first and the second processor (101, 102) is operable in a transmit mode (301) for transmitting data to the respective other processor (101, 102) by controlling the second logic output pin (12, 22) to provide a logic data signal (DAT) indicating a sequence of data bits (D7-D0) and controlling the first logic output pin (11, 21) to provide a logic clock signal (CLK) with state transitions indicating when the logic data signal (DAT) indicates the values of the individual data bits (D7-D0) in the sequence.Each of the first and the second processor (101, 102) is operable in a receive mode (401) for receiving data from the respective other processor (101, 102) by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal (CLK) received on the second logic input pin (14, 24).The apparatus (109) is characterized in that each of the first and the second processor (101, 102) further is configured to: in dependence on being in the receive mode (401) and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal (CTS) indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal (ACK) with state transitions indicating successful reception of individual data bits (D7-D0); and in dependence on being in the transmit mode (301), delay transmission of the first data bit (D7-D0) in the sequence until determining that the logic clear-to-send signal (CTS) indicates the ability to receive data by the respective other processor (101, 102) and delay transmission of each subsequent data bit (D7-D0) in the sequence until determining a state transition of the logic data-acknowledge signal (ACK) that indicates successful reception of the respective previous data bit (D7-D0) by the respective other processor (101, 102).

10. 发明申请

US20180139076A1 LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER 审中-公开
公开(公告)号：US20180139076A1
公开(公告)日：2018-05-17
申请号：US15795927
申请日：2017-10-27
申请人： Yuji WATABE , Hiroaki KYOGOKU , Nobunari TSUKAMOTO
发明人： Yuji WATABE , Hiroaki KYOGOKU , Nobunari TSUKAMOTO
IPC分类号： H04L25/02 , H03K19/0185 , H03L7/081 , H03L7/093 , G06F1/06 , H03K5/135 , H03K17/687
CPC分类号： H04L25/028 , G06F1/06 , H03K5/135 , H03K17/687 , H03K19/018528 , H03L7/081 , H03L7/093 , H04L25/0272
摘要： A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.

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