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1. 发明授权

US11552748B2 Communication channel calibration for drift conditions 有权
公开(公告)号：US11552748B2
公开(公告)日：2023-01-10
申请号：US17386111
申请日：2021-07-27
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00 , H04L1/24 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00 , G11C7/04 , H04L7/033
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

2. 发明申请

US20200351038A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 审中-公开
公开(公告)号：US20200351038A1
公开(公告)日：2020-11-05
申请号：US16861164
申请日：2020-04-28
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L1/24 , H04L7/00 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

3. 发明申请

US20200258555A1 Memory Controllers, Systems, and Methods Supporting Multiple Request Modes 审中-公开
公开(公告)号：US20200258555A1
公开(公告)日：2020-08-13
申请号：US16790183
申请日：2020-02-13
申请人： Rambus Inc.
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G11C7/10 , G06F13/16 , G11C5/06
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

4. 发明授权

US10593390B2 Dynamic memory supporting simultaneous refresh and data-access transactions 有权
公开(公告)号：US10593390B2
公开(公告)日：2020-03-17
申请号：US15785918
申请日：2017-10-17
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego
IPC分类号： G06F12/00 , G11C11/406 , G06F13/16
摘要： Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

5. 发明授权

US10523344B2 Periodic calibration for communication channels by drift tracking 有权
公开(公告)号：US10523344B2
公开(公告)日：2019-12-31
申请号：US16393817
申请日：2019-04-24
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04L7/00 , H04L7/04 , H04B17/11 , H04B17/21 , H04L27/00 , H04L7/10 , H04B17/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

6. 发明授权

US10236051B2 Memory controller 有权
公开(公告)号：US10236051B2
公开(公告)日：2019-03-19
申请号：US15666496
申请日：2017-08-01
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C11/24 , G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G06F1/06 , G06F1/12 , G06F3/06 , G11C7/04
摘要： A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

7. 发明授权

US09667359B2 Periodic calibration for communication channels by drift tracking 有权
公开(公告)号：US09667359B2
公开(公告)日：2017-05-30
申请号：US14718019
申请日：2015-05-20
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B17/11 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00 , H04B17/00 , H04B17/21
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

8. 发明申请

US20160056948A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
公开(公告)号：US20160056948A1
公开(公告)日：2016-02-25
申请号：US14932192
申请日：2015-11-04
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

9. 发明授权

US09257151B2 Printed-circuit board supporting memory systems with multiple data-bus configurations 有权
标题翻译：支持具有多种数据总线配置的存储系统的印刷电路板
公开(公告)号：US09257151B2
公开(公告)日：2016-02-09
申请号：US14306304
申请日：2014-06-17
申请人： Rambus Inc.
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G11C5/04 , G06F12/06 , G06F12/04 , G06F13/16 , G11C5/02 , G11C5/06 , G11C7/10 , G11C11/408 , G11C11/4097 , H05K1/14 , G11C8/06 , H05K1/11
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了支持存储器系统的印刷电路板（PCB），其中存储器核心组织随设备宽度而变化。 PCB包括存储器控制器安装位置和模块连接器以接收相应的存储器模块。每个模块连接器通过不连接到任何其他模块连接器的相应的一组系统数据线直接连接到控制器安装位置。系统数据线也直接在模块连接器之间扩展，以支持具有不同数量模块的存储器配置。存储器系统支持宽数据宽度的一个存储器模块或较窄数据宽度的多个存储器模块。访问的物理存储器组的数量随设备数据宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

10. 发明授权

US09160466B2 Periodic calibration for communication channels by drift tracking 有权
标题翻译：通过漂移跟踪定期通信通道
公开(公告)号：US09160466B2
公开(公告)日：2015-10-13
申请号：US14535006
申请日：2014-11-06
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B17/00 , H04B3/46 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00 , H04Q1/20
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

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