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51. 发明授权

US08826252B2 Using vector atomic memory operation to handle data of different lengths 有权
标题翻译：使用向量原子内存操作来处理不同长度的数据
公开(公告)号：US08826252B2
公开(公告)日：2014-09-02
申请号：US12483908
申请日：2009-06-12
申请人： Terry D. Greyzck
发明人： Terry D. Greyzck
IPC分类号： G06F9/45 , G06F15/00 , G06F9/30 , G06F12/00 , G06F9/38
CPC分类号： G06F9/30029 , G06F8/445 , G06F9/3004 , G06F9/30087 , G06F9/3834
摘要： A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts.
摘要翻译：一种编译程序代码的系统和方法，其中所述程序代码包括对存储在计算机系统的存储器中的数据元素阵列的操作。对程序代码进行扫描，以对除了有限数量的向量支持的数据长度以外的长度的数据进行操作。该方程然后用矢量化机器可执行代码替换，其中机器可执行代码包括嵌套循环，并且其中嵌套循环包括外部循环和虚拟内部循环。外部环路将方程分解成长度为N的多个环，其中N是大于1的整数。虚拟内环执行对应于N长度循环的向量操作以形成长度为N的结果向量，其中虚拟内部循环包括用于解决错误冲突的一个或多个向量原子存储器操作（AMO）指令。

52. 发明申请

US20140244657A1 DYNAMIC GRAPH SYSTEM FOR A SEMANTIC DATABASE 有权
标题翻译：用于语义数据库的动态图形系统
公开(公告)号：US20140244657A1
公开(公告)日：2014-08-28
申请号：US13777884
申请日：2013-02-26
申请人： CRAY INC.
发明人： David Mizell
IPC分类号： G06F17/30
CPC分类号： G06T11/206 , G06F17/30321 , G06F17/30958
摘要： A method and system in a computer system for dynamically providing a graphical representation of a data store of entries via a matrix interface is disclosed. A dynamic graph system provides a matrix interface that exposes to an application program a graphical representation of data stored in a data store such as a semantic database storing triples. To the application program, the matrix interface represents the graph as a sparse adjacency matrix that is stored in compressed form. Each entry of the data store is considered to represent a link between nodes of the graph. Each entry has a first field and a second field identifying the nodes connected by the link and a third field with a value for the link that connects the identified nodes. The first, second, and third fields represent the rows, column, and elements of the adjacency matrix.
摘要翻译：公开了一种用于通过矩阵接口动态地提供条目的数据存储的图形表示的计算机系统中的方法和系统。动态图系统提供了一个矩阵接口，向应用程序公开存储在数据存储器中的数据的图形表示，例如存储三元组的语义数据库。对于应用程序，矩阵接口将图形表示为以压缩形式存储的稀疏邻接矩阵。数据存储的每个条目被认为表示图形的节点之间的链接。每个条目具有标识通过链路连接的节点的第一字段和第二字段，以及连接所识别的节点的链接的值的第三字段。第一，第二和第三字段表示邻接矩阵的行，列和元素。

53. 发明申请

US20140081934A1 DYNAMIC UPDATES TO A SEMANTIC DATABASE USING FINE-GRAIN LOCKING 有权
标题翻译：动态更新到使用细粒度锁定的语义数据库
公开(公告)号：US20140081934A1
公开(公告)日：2014-03-20
申请号：US13623688
申请日：2012-09-20
申请人： CRAY INC.
发明人： David Mizell
IPC分类号： G06F17/30
CPC分类号： G06F17/30348 , G06F17/30321 , G06F17/3033 , G06F17/30917
摘要： A system for updating an index into a tuple table of tuples is provided. An indexing system updates an index into a tuple table using fine-grain locking of the index. The index includes a values table with an entry for each index value of an index field that references a value-tuple table that includes, for each tuple with the index value, a row that identifies a tuple of the tuple table with that indexed value. After a new tuple is added to the tuple table with a value, the index is updated by locking the entry in the values table, updating the value-tuple table for the value, and then unlocking the entry. When the index is accessed for locating tuples with a value, the accessor locks the entry in the values table for the value, uses the value-tuple table to locate the tuples, and unlocks the entry.
摘要翻译：提供了一种用于将索引更新为元组的元组表的系统。索引系统使用索引的细粒度锁定将索引更新为元组表。索引包括一个值表，其中包含索引字段的每个索引值的条目，该索引字段引用一个值元组表，该值包含具有索引值的每个元组，该行用于标识具有该索引值的元组表的元组。在使用值添加到元组表的新元组之后，通过将值表中的条目锁定，更新该值的值 - 元组表，然后解锁该条目来更新该索引。当访问用于定位具有值的元组的索引时，访问器将该值锁定在值表中的值，使用value-tuple表来定位元组，并解锁该条目。

54. 发明授权

US08654489B2 Method and apparatus for switched electrostatic discharge protection 有权
标题翻译：开关静电放电保护方法及装置
公开(公告)号：US08654489B2
公开(公告)日：2014-02-18
申请号：US13175387
申请日：2011-07-01
申请人： Raymond J. Farbarik , Jeremy Stephens , Gerald J. Twomey
发明人： Raymond J. Farbarik , Jeremy Stephens , Gerald J. Twomey
IPC分类号： H02H3/20 , H02H9/04
CPC分类号： H02H9/046
摘要： One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.
摘要翻译：一个实施例包括集成电路，其包括输入电路，包括第一阳极和第一阴极的第一二极管，其中第一阴极耦合到第一电压，第一阳极经由第一机械开关耦合到节点处的输入电路，第二二极管，包括第二阳极和第二阴极，其中第二阴极经由第二机械开关耦合到节点，第二阳极耦合到地和耦合到集成电路和节点之间的输入电路的电阻器，其中在第一操作模式中，第一机械开关和第二机械开关导通，并且在第二操作模式中，第一和第二机械开关是不导通的。

55. 发明授权

US08601236B2 Configurable vector length computer processor 有权
标题翻译：可配置向量长度计算机处理器
公开(公告)号：US08601236B2
公开(公告)日：2013-12-03
申请号：US13409033
申请日：2012-02-29
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

56. 发明授权

US08386750B2 Multiprocessor system having processors with different address widths and method for operating the same 有权
标题翻译：具有不同地址宽度的处理器的多处理器系统及其操作方法
公开(公告)号：US08386750B2
公开(公告)日：2013-02-26
申请号：US12263321
申请日：2008-10-31
申请人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
发明人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
IPC分类号： G06F12/08
CPC分类号： G06F12/0284
摘要： A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.
摘要翻译：多处理器计算机系统具有多个具有第一可寻址存储器空间的第一处理器和具有第二可寻址存储器空间的多个第二处理器。第二可寻址存储器空间的尺寸与第一可寻址存储器空间不同，并且第一可寻址存储器空间和第二可寻址存储器空间包括相同公共地址空间的一部分。

57. 发明授权

US08347176B2 Method and apparatus for memory read-refresh, scrubbing and variable-rate refresh 有权
标题翻译：用于存储器读取刷新，擦除和可变速率刷新的方法和装置
公开(公告)号：US08347176B2
公开(公告)日：2013-01-01
申请号：US13237676
申请日：2011-09-20
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读刷新（也称为分布式刷新）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取每一行存储器，其中来自行内不同列的数据为在随后的读取刷新循环中读取，直到读取每个列地址的所有行，如果找到，则清除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

58. 发明授权

US08332596B2 Multiple error management in a multiprocessor computer system 有权
标题翻译：多处理器计算机系统中的多错误管理
公开(公告)号：US08332596B2
公开(公告)日：2012-12-11
申请号：US12484164
申请日：2009-06-12
申请人： Clayton D. Andreasen
发明人： Clayton D. Andreasen
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724
摘要： An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.
摘要翻译：错误消息处理缓冲器包括第一缓冲器和第二缓冲器。第一索引与第一缓冲器相关联，第二索引与第二缓冲器相关联。缓冲器控制器可用于在缓冲器中写入和读取消息，使得消息被写入具有小于缓冲器大小的缓冲器索引值的第一和第二缓冲器的缓冲器，并且从第一和第二缓冲器中的另一个读取缓冲器，另一个缓冲器的索引值大于或等于缓冲区大小。

59. 发明授权

US08296771B2 System and method for mapping between resource consumers and resource providers in a computing system 有权
标题翻译：在计算系统中资源使用者和资源提供者之间进行映射的系统和方法
公开(公告)号：US08296771B2
公开(公告)日：2012-10-23
申请号：US10643740
申请日：2003-08-18
申请人： Stephan Kurt Gipp
发明人： Stephan Kurt Gipp
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/5016
摘要： A system and method for allocating system resources is described herein. In one embodiment, the method comprises creating, in a computer system, a resource consumer and assigning the resource consumer one of a set of flavors. The method further includes determining whether the resource consumer is limited to receiving resources from a certain one of a set of resource providers, wherein each of the set of resource providers has one of the set of flavors. The method further includes marking a field to indicate that the resource consumer is limited to receiving resources from the certain one of the set of resource providers, if the resource consumer is limited to receiving resources from the certain one of the set of resource providers. The method further includes allocating a resource to the resource consumer from one of the set of resource providers whose flavor matches the flavor assigned to the resource consumer.
摘要翻译：这里描述了用于分配系统资源的系统和方法。在一个实施例中，该方法包括在计算机系统中创建资源消费者并且分配资源消费者一组风格之一。该方法还包括确定资源消费者是否被限于从一组资源提供者中的某一个接收资源，其中资源提供者集合中的每一个具有一组风格之一。该方法还包括：如果资源消费者被限制为从资源提供者集合中的某一个接收资源，则标记字段以指示资源消费者被限制为从该资源提供者集合中的某一个接收资源。该方法还包括从资源消耗者的风味与分配给资源消费者的风味相匹配的一组资源提供者中的一个资源消费者分配资源。

60. 发明申请

US20120198470A1 COMPACT NODE ORDERED APPLICATION PLACEMENT IN A MULTIPROCESSOR COMPUTER 有权
标题翻译：在多处理器计算机中的紧凑的节点订购应用程序
公开(公告)号：US20120198470A1
公开(公告)日：2012-08-02
申请号：US13361551
申请日：2012-01-30
申请人： Carl Albing , Norman Troullier, JR.
发明人： Carl Albing , Norman Troullier, JR.
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A multiprocessor computer system comprises a plurality of nodes, wherein the nodes are ordered using a snaking dimension-ordered numbering. An application placement module is operable to place an application in nodes with preference given to nodes ordered near one another.
摘要翻译：多处理器计算机系统包括多个节点，其中使用蛇形维数排序对节点进行排序。应用程序放置模块可操作以将应用放置在具有优先于彼此排序的节点的节点中。

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