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1. 发明授权

US08347176B2 Method and apparatus for memory read-refresh, scrubbing and variable-rate refresh 有权
标题翻译：用于存储器读取刷新，擦除和可变速率刷新的方法和装置
公开(公告)号：US08347176B2
公开(公告)日：2013-01-01
申请号：US13237676
申请日：2011-09-20
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读刷新（也称为分布式刷新）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取每一行存储器，其中来自行内不同列的数据为在随后的读取刷新循环中读取，直到读取每个列地址的所有行，如果找到，则清除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

2. 发明授权

US08230305B2 Extended single-bit error correction and multiple-bit error detection 有权
标题翻译：扩展单位纠错和多位错误检测
公开(公告)号：US08230305B2
公开(公告)日：2012-07-24
申请号：US12417390
申请日：2009-04-02
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： H03M13/00
CPC分类号： H03M13/05 , G06F11/1008 , H03M13/19
摘要： Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.
摘要翻译：一些实施例包括如果多比特错误包括属于多个数据比特组中的一个特定组的多个错误数据比特，并且如果不存在，则防止错误识别和忽略多比特错误中的至少一个的装置和方法的多个组中的其他组的错误。

3. 发明授权

US08139434B2 Methods and apparatus for voltage sensing and reporting 有权
标题翻译：电压检测和报告的方法和装置
公开(公告)号：US08139434B2
公开(公告)日：2012-03-20
申请号：US12604653
申请日：2009-10-23
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G01R19/16552 , G11C5/14
摘要： Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.
摘要翻译：半导体器件包括用于感测与半导体器件的操作电路相关联的工作电压的至少一个电压传感器。所述至少一个电压传感器被配置为产生指示所述工作电压的状态的信号。监测半导体器件中的电压的方法包括确定半导体器件中的操作电路的工作电压的大小。可以产生指示工作电压的状态的信号。

4. 发明授权

US08046628B2 Failure recovery memory devices and methods 有权
标题翻译：故障恢复存储器件和方法
公开(公告)号：US08046628B2
公开(公告)日：2011-10-25
申请号：US12479530
申请日：2009-06-05
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： G06F11/00
CPC分类号： G06F11/073 , G06F11/1044
摘要： Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.
摘要翻译：描述了包括串行链接存储器件的存储器件和方法。在所示的一个或多个配置中，存储器设备的串行链包括多个存储器设备，以及在链末端的错误恢复设备。在所示的一个配置中，存储器件的串行链包括一系列器件，其中每个器件是堆叠的管芯存储器件。描述了在写入操作和数据恢复操作中使用错误恢复设备的方法。

5. 发明授权

US08028198B2 Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory 有权
标题翻译：用于半导体存储器的检测，感测和报告功能的装置，方法和装置
公开(公告)号：US08028198B2
公开(公告)日：2011-09-27
申请号：US11830495
申请日：2007-07-30
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： G06F11/00
CPC分类号： G11C7/04 , G11C7/1006 , G11C7/1045 , G11C2029/0409
摘要： Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.
摘要翻译：公开了用于存储器件的方法，装置和系统。在一个实施例中，公开了可以包括可操作地耦合到模式寄存器，命令输入和地址输入的命令错误模块的存储器件。命令错误模块可以被配置为检测无效命令序列并向输出信号报告错误指示。另外，存储器件可以包括可操作地耦合到模式寄存器和参考电压的温度传感器。温度传感器可以被配置为感测设备温度并报告温度状态。此外，存储器件可以并入到可以包括在电子系统中的存储器模块中。

6. 发明授权

US07826996B2 Memory-daughter-card-testing apparatus and method 有权
标题翻译：记忆子卡测试仪和方法
公开(公告)号：US07826996B2
公开(公告)日：2010-11-02
申请号：US11679175
申请日：2007-02-26
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01C31/00 , G06F11/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一个MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

7. 发明申请

US20090037778A1 DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY 有权
标题翻译：用于半导体存储器的检测，传感和报告功能的器件，方法和装置
公开(公告)号：US20090037778A1
公开(公告)日：2009-02-05
申请号：US11830495
申请日：2007-07-30
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： G06F11/00 , G01K7/00
CPC分类号： G11C7/04 , G11C7/1006 , G11C7/1045 , G11C2029/0409
摘要： Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.
摘要翻译：公开了用于存储器件的方法，装置和系统。在一个实施例中，公开了可以包括可操作地耦合到模式寄存器，命令输入和地址输入的命令错误模块的存储器件。命令错误模块可以被配置为检测无效命令序列并向输出信号报告错误指示。另外，存储器件可以包括可操作地耦合到模式寄存器和参考电压的温度传感器。温度传感器可以被配置为感测设备温度并报告温度状态。此外，存储器件可以并入到可以包括在电子系统中的存储器模块中。

8. 发明授权

US07184916B2 Apparatus and method for testing memory cards 有权
标题翻译：用于测试存储卡的装置和方法
公开(公告)号：US07184916B2
公开(公告)日：2007-02-27
申请号：US10850044
申请日：2004-05-19
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G06F19/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

9. 发明授权

US5396641A Reconfigurable memory processor 失效
标题翻译：可重构内存处理器
公开(公告)号：US5396641A
公开(公告)日：1995-03-07
申请号：US73978
申请日：1993-06-08
申请人： Kenneth W. Iobst , David R. Resnick , Kenneth R. Wallgren
发明人： Kenneth W. Iobst , David R. Resnick , Kenneth R. Wallgren
IPC分类号： G06F7/50 , G06F7/509 , G06F7/575 , G06F11/10 , G06F12/00 , G06F12/06 , G06F12/16 , G06F15/78 , G06F15/80 , G06F17/16 , G11C29/00 , G11C29/42 , G06F13/00
CPC分类号： G06F7/509 , G06F11/1016 , G06F15/7821 , G06F15/7842 , G06F15/8015 , G06F7/575
摘要： A process in memory chip has been designed to combine memory and computation on the same integrated circuit in a way that makes use of the bandwidth that results from the combination. The chip contains multiple single-bit computational processors that are all driven in parallel. Error correction logic is also incorporated into the chip to detect and correct errors in memory, data as they occur.
摘要翻译：存储器芯片中的一个过程被设计为将存储器和计算结合在同一集成电路上，以便利用由组合产生的带宽。该芯片包含多个并行驱动的单位计算处理器。错误校正逻辑也被并入到芯片中以检测和纠正存储器，数据发生时的错误。

10. 发明授权

US4791602A Soft programmable logic array 失效
标题翻译：软可编程逻辑阵列
公开(公告)号：US4791602A
公开(公告)日：1988-12-13
申请号：US935054
申请日：1986-11-21
申请人： David R. Resnick
发明人： David R. Resnick
IPC分类号： H03K19/173 , H03K19/00 , G06F7/38
CPC分类号： H03K19/1737 , H03K19/1733
摘要： A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices. The seventh and eighth logic levels are represented by another level of functional elements and pass-through/hold devices. Finally, the output logic is a plurality of output enable gates connected to tri-state buffers. The tri-state buffers may be high, low or floating. The output enable gate functions to either cause a direct pass-through of the input logic signal or activates the tri-state buffer to operate on the output logic level. The logic array is configured and controlled by input control bits to characterize the operation of each functional element and pass-through/hold device so that it functions either to produce combinations of input logic levels or to achieve particular logic states or a combination of the two functional modes. The output enable gates are controlled like the functional elements to either enable or disable tri-state control of the output buffers.
摘要翻译：可编程逻辑阵列由两种类型的独立可控逻辑构建块和特殊输出逻辑构成，以执行所需的逻辑功能。第一个构建块是能够执行其输入数据的任何逻辑功能以创建输出数据的功能元件。所显示的功能元件基于三个输入和单个输出。构建块的第二基本类型是直通/保持装置，其可以直接通过其输入作为输出，或者可以锁存和保持输入直到定时。第一类型和第二类型的元素的多个逻辑等级或等级互连，使得输出可以是输入的各种功能。这里描述的逻辑阵列具有第一和第二逻辑电平，其由功能元件组成，后面是第三级的通过/保持设备。第四和第五逻辑电平是功能元件和通过/保持设备。第七和第八逻辑电平由另一级功能元件和直通/保持装置表示。最后，输出逻辑是连接到三态缓冲器的多个输出使能门控。三态缓冲器可以是高，低或漂浮。输出使能门功能可以引起输入逻辑信号的直接传递，或者激活三态缓冲器以在输出逻辑电平上工作。逻辑阵列由输入控制位配置和控制，以表征每个功能元件和直通/保持装置的操作，使得它可以产生输入逻辑电平的组合或实现特定的逻辑状态或二者的组合功能模式。像功能元件一样控制输出使能门，以启用或禁用输出缓冲器的三态控制。

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