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51. 发明授权

US4719370A BiMOS high speed inverter circuit 失效
标题翻译： BiMOS高速逆变电路
公开(公告)号：US4719370A
公开(公告)日：1988-01-12
申请号：US804473
申请日：1985-12-04
申请人： Yasuhiro Sugimoto
发明人： Yasuhiro Sugimoto
IPC分类号： H03K19/08 , H03K17/04 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/02 , H03K5/01 , H03K5/12 , H03K17/60
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： An improved inverter circuit capable of attaining complete swift inversion is shown. The circuit comprises bipolar transistors (27, 29) by which an inverted output takes a level near the rated level and MOS transistors (21, 23) by which the inverted output reaches the rated level from the near level. The MOS transistor (21, 23) is driven by a bipolar transistor (31) and possesses high current driving capacity with its large dimensions of the gate region.
摘要翻译：示出了能够实现完全快速反转的改进的逆变器电路。电路包括双极晶体管（27,29），反相输出端接近额定电平，MOS晶体管（21,23）通过该晶体管反相输出从近电平达到额定电平。 MOS晶体管（21,23）由双极晶体管（31）驱动，并具有大的栅极区域的大电流驱动能力。

52. 发明授权

US4717847A TTL compatible CMOS input buffer 失效
标题翻译： TTL兼容CMOS输入缓冲器
公开(公告)号：US4717847A
公开(公告)日：1988-01-05
申请号：US728271
申请日：1985-04-29
申请人： Joseph G. Nolan
发明人： Joseph G. Nolan
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/0944 , H03K19/02 , H03K17/60 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/00384 , H03K19/017518 , H03K19/09448
摘要： A TTL to CMOS buffer includes first and second field effect transistors of opposite conductivity types connected to form an inverter. The main current conducting path of a third transistor is connected in series with the current conducting paths of the first and second transistors. The control terminal of the third transistor is connected to a power supply. In a preferred embodiment, a bipolar transistor is connected between the output of the inverter circuit and the buffer output. The bipolar transistor may be a common parasitic device produced in conjunction with the CMOS circuits. This transistor offers a degree of temperature compensation to the buffer circuit output.
摘要翻译： TTL到CMOS缓冲器包括连接形成反相器的相反导电类型的第一和第二场效应晶体管。第三晶体管的主电流传导路径与第一和第二晶体管的电流传导路径串联连接。第三晶体管的控制端子连接到电源。在优选实施例中，双极晶体管连接在逆变器电路的输出端和缓冲器输出端之间。双极晶体管可以是与CMOS电路一起生产的常见寄生器件。该晶体管为缓冲电路输出提供一定程度的温度补偿。

53. 发明授权

US4703204A Logic coincidence gate and logic sequential circuits using said coincidence gate 失效
标题翻译：使用所述符合门的逻辑符合门和逻辑顺序电路
公开(公告)号：US4703204A
公开(公告)日：1987-10-27
申请号：US807731
申请日：1985-12-11
申请人： Ngu T. Pham
发明人： Ngu T. Pham
IPC分类号： H03K19/20 , H03K19/21 , H03K19/017 , H03K19/02 , H03K19/092 , H03K19/094
CPC分类号： H03K19/217
摘要： The invention relates to a coincidence gate, whose output only changes state if the inputs are of the same logic level. It has two parallel-connected NOT circuits, each constituted by a transistor, whose source is at earth and the drain supplied by a resistor, the gates constituting the inputs of the gate. The two resistors are identical saturated resistors and the first NOT circuit is supplied from a fixed voltage, whereas the second NOT circuit is supplied across a Schottky diode connected in the forward direction from the point common to the first saturated resistor and to the drain of the first transistor. The point common to the Schottky diode and the second saturated resistor constitutes the output of the coincidence gate. Application to sequential logic circuits.
摘要翻译：本发明涉及符合门，其输出仅在输入具有相同逻辑电平时才改变状态。它具有两个并联的NOT电路，每个都由晶体管构成，晶体管源源于地，漏极由电阻提供，栅极构成栅极的输入。两个电阻是相同的饱和电阻，第一个NOT电路由一个固定的电压提供，而第二个NOT电路是从正向连接的肖特基二极管上提供的，该肖特基二极管与第一个饱和电阻相同的点连接到第一晶体管。肖特基二极管和第二饱和电阻共同点构成了重合门的输出。应用于顺序逻辑电路。

54. 发明授权

US4698524A MESFET logic using integral diode level shifting 失效
标题翻译： MESFET逻辑采用积分二极管电平转换
公开(公告)号：US4698524A
公开(公告)日：1987-10-06
申请号：US886596
申请日：1986-07-16
申请人： Mark R. Plagens
发明人： Mark R. Plagens
IPC分类号： A61K8/67 , A61Q19/00 , A61Q19/08 , H03K19/003 , H03K19/0952 , H03K19/094 , H03K19/02 , H03K19/092
CPC分类号： A61K8/671 , A61Q19/004 , A61Q19/08 , H03K19/00361 , H03K19/0952
摘要： A semiconductor logic circuit utilizing level shifting of input transistors away from a reference voltage level but shifting the output toward the reference voltage level to increase noise margin. The input signals may switch both the input transistors and the output transistors.
摘要翻译：半导体逻辑电路利用输入晶体管的电平移动远离参考电压电平，但将输出移向参考电压电平以增加噪声容限。输入信号可以切换输入晶体管和输出晶体管。

55. 发明授权

US4125784A Fail-safe or gate 失效
标题翻译：故障安全或门禁
公开(公告)号：US4125784A
公开(公告)日：1978-11-14
申请号：US819514
申请日：1977-07-27
申请人： John R. Harrison
发明人： John R. Harrison
IPC分类号： H03K19/007 , H03K19/02 , H03K19/30
CPC分类号： H03K19/007
摘要： A fail-safe "OR" logic gate circuit which includes at least a first and a second level detector each of which has a voltage breakdown device and an oscillating circuit, a separate resonant tank circuit each of which is tuned to substantially the same frequency and being loosely coupled between each other, an amplifying circuit coupled to the output of each oscillating circuit, and a regulating-rectifying circuit coupled to the output of the amplifying circuit and producing a d.c. output signal when a d.c. input signal causes either or both of the voltage breakdown devices to break down and to exhibit a low impedance for causing the respective oscillating circuits to oscillate and supply a.c. signals to the amplifying circuit for rectification by the regulating-rectifying circuit.
摘要翻译：一种故障安全的“或”逻辑门电路，其至少包括第一和第二电平检测器，每个检测器具有电压击穿器件和振荡电路，每个谐振回路被调谐到基本相同的频率，彼此松耦合，耦合到每个振荡电路的输出的放大电路和耦合到放大电路的输出的调节整流电路，并产生直流输出信号时直流输入信号导致电压击穿器件中的任一个或两者分解并且呈现低阻抗，以使相应的振荡电路振荡并提供直流。通过调节整流电路向放大电路发送信号以进行整流。

56. 发明授权

US3868515A Josephson device threshold gates 失效
标题翻译：约瑟夫森器件阈值门
公开(公告)号：US3868515A
公开(公告)日：1975-02-25
申请号：US31981172
申请日：1972-12-29
申请人： IBM
发明人： LANDMAN BERNARD S
IPC分类号： H03K19/195 , H03K19/02 , H03K3/38 , H03K19/20
CPC分类号： H03K19/1952 , Y10S505/858
摘要： Threshold logic gates are provided using Josephson devices to perform the weighting and threshold functions. The input currents are provided as control currents to vary the critical switching currents of respective series connected Josephson devices. A logic 1 input switches the associated Josephson device or devices from the V 0 state to the V Delta state. An alternate parallel path is provided. The alternate path carries a current which is effectively the sum of the weighted logic inputs. A further Josephson device is positioned to be influenced by the current in said alternate path whereby the further Josephson device switches from the V 0 state to the V Delta state when the threshold function is achieved.
摘要翻译：使用约瑟夫逊器件提供阈值逻辑门来执行加权和阈值函数。输入电流被提供为控制电流，以改变各个串联的约瑟夫逊器件的关键开关电流。逻辑1输入将相关联的约瑟夫逊器件或器件从V = 0状态切换到V = DELTA状态。提供了一个交替的并行路径。备用路径携带有效地加权逻辑输入之和的电流。进一步的约瑟夫逊装置被定位成受到所述交替路径中的电流的影响，由此当实现阈值功能时，另外的约瑟夫逊装置从V = 0状态切换到V = DELTA状态。

57. 发明授权

US3621306A Controlled gunn-effect device 失效
标题翻译：控制的枪管装置
公开(公告)号：US3621306A
公开(公告)日：1971-11-16
申请号：US3621306D
申请日：1968-09-23
申请人： TELEFUNKEN PATENT
发明人： SCHICKLE GERHARD
IPC分类号： H01L47/00 , H03B9/12 , H03B19/00 , H03K3/02 , H03K19/02 , H03K19/24
CPC分类号： H03K19/02 , H01L47/00 , H03B9/12 , H03B19/00 , H03K3/02
摘要： A Gunn-effect device in which the active layer of the semiconductor body is provided with a suitable recess, hole or opening which extends through the active layer and which directly or indirectly affects the high electric field zone in the crystal.
摘要翻译：一种耿氏效应器件，其中半导体主体的有源层设置有合适的凹部，孔或开口，其在与载流子的漂移运动方向垂直的方向上延伸穿过有源层。优选地，孔内提供至少一个触点，其与设置在有源层的相对边缘上的另一触点配合。半导体本体的有源层例如可以是圆形，矩形或椭圆形，并且如果需要，可以包括多对触点，每对触点一个在孔内，另一个触点位于该边缘上活动层

58. 发明授权

US3594618A Electronic logic element 失效
标题翻译：电子逻辑元件
公开(公告)号：US3594618A
公开(公告)日：1971-07-20
申请号：US3594618D
申请日：1968-06-21
申请人： NAT RES DEV
发明人： HARTNAGEL HANS LUDWIG
IPC分类号： G06F7/50 , G06F7/504 , G11C19/28 , H01L47/00 , H01L47/02 , H03K19/02 , H03M1/44 , H01L9/00
CPC分类号： G06F7/504 , G11C19/28 , H01L47/00 , H01L47/02 , H03K19/02 , H03M1/44
摘要： A logic element is described utilizing a travelling field domain phenomenon, such as the Gunn effect, which occurs in a body of material when a field is produced in the body above a first threshold value to nucleate a domain and is maintained above a second threshold value to sustain the domain. A plurality of contact means are carried on the body together with output means for detecting a field domain in the body and for deriving an output signal therefrom, and the arrangement is such that application between a predetermined number of the contact means of a potential just sufficient to create a field domain in the body produces an output signal at the output means, but the application of the same potential between a number of the contact means greater than the said predetermined number does not produce an output signal at the output means. One arrangement of the invention provides a comparator logic element having one primary electrode, and two secondary input electrodes, and a number of circuits utilizing this comparator are described.

59. 发明授权

US3452213A Microwave logic circuit 失效
标题翻译：微波逻辑电路
公开(公告)号：US3452213A
公开(公告)日：1969-06-24
申请号：US3452213D
申请日：1965-10-22
申请人： IBM
发明人： GAMBLIN RODGER L , LORD PHILIP A , MARCUS MITCHELL P , TUNIS CYRIL J
IPC分类号： G06F15/18 , G11C11/06 , H03K19/00 , H03K19/02
CPC分类号： G11C11/0605 , G06N99/005 , H03K19/00 , H03K19/02

60. 发明授权

US10733524B1 Quantum D-state AC-Stark shift gate 有权
公开(公告)号：US10733524B1
公开(公告)日：2020-08-04
申请号：US16717535
申请日：2019-12-17
申请人： Honeywell International Inc.
发明人： Michael Feig , Jonathon Sedlacek , Mark Kokish , Christopher Langer , John Gaebler , Daniel Stack , Bryce J. Bjork , Grahame Vittorini , David Hayes
IPC分类号： G06N10/00 , H03K19/02
摘要： A quantum computing D-state AC-Stark shift gate system comprises at least one gate manipulation source and one or more ions trapped in an ion trap. The at least one gate manipulation source is configured to generate a first gate manipulation signal and a second gate manipulation signal. The first and second gate manipulation signals couple an ion between a set of S-states and a set of D-states. The first and second gate manipulation signals apply a force to an ion of the one or more ions that is dependent on the internal state of the ion. The first and second gate manipulation signals are configured to couple internal states of the ions to their motional state without appreciably altering a population of the ions within the set of S-states.

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