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1. 发明授权

US11387405B2 Resonance rotating spin-transfer torque memory device 有权
公开(公告)号：US11387405B2
公开(公告)日：2022-07-12
申请号：US16201590
申请日：2018-11-27
申请人： Carnegie Mellon University
发明人： Jian-Gang Zhu
IPC分类号： H01L43/02 , H01L43/10 , H01L27/22 , H03B15/00 , H01F10/32 , G11C11/06 , G11C11/16
摘要： A memory device includes a plurality of layers forming a stack. The plurality of layers include a spin polarization layer having a magnetic anisotropy approximately perpendicular to a plane of the spin polarization layer, an antiferromagnetic layer having an antiferromagnetic material, a ferromagnetic layer that is exchange coupled to the antiferromagnetic layer, where the antiferromagnetic layer is between the ferromagnetic layer and the spin polarization layer, and a storage layer having a magnetization direction that indicates a memory state of the storage layer. The memory state is switched by an amount of current through the stack. The spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer are configured to reduce the amount of current through the stack for switching the magnetization direction of the storage layer relative to an amount of current through a memory device without the spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer.

2. 发明授权

US10373673B2 Semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US10373673B2
公开(公告)日：2019-08-06
申请号：US15614714
申请日：2017-06-06
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JoongShik Shin , Byoungil Lee , Hyunmog Park , Euntaek Jung
IPC分类号： H01L29/76 , G11C11/408 , G11C8/08 , G11C8/12 , G11C11/06 , H01L21/8239 , H01L23/528 , G11C8/14 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

3. 发明授权

US09224487B2 Semiconductor memory read and write access 有权
标题翻译：半导体存储器读写访问
公开(公告)号：US09224487B2
公开(公告)日：2015-12-29
申请号：US13749246
申请日：2013-01-24
申请人： Spansion LLC
发明人： Kaoru Mori , Toshiya Uchida
IPC分类号： G11C11/06 , G11C16/26 , G11C7/18 , G11C7/22 , G11C16/24 , G11C16/32
CPC分类号： G11C16/26 , G11C7/18 , G11C7/227 , G11C16/24 , G11C16/32
摘要： A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.
摘要翻译：半导体存储器包括读出放大器，其响应于读出放大器使能信号的激活而操作，并且根据位线的电压确定保持在非易失性存储器单元中的逻辑，该电压随着流过真实单元晶体管的单元电流而变化耦合在第一节点和地线之间的复制单元晶体管，以及定时产生单元。当通过复制单元晶体管耦合到接地线的第一节点从高电平变为低电平时，定时生成单元激活读出放大器使能信号。复制单元晶体管包括接收恒定电压的控制栅极和耦合到控制栅极的浮置栅极。因此，可以根据存储单元的电特性来最佳地设置读出放大器的激活定时。

4. 发明授权

US09070442B2 Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods 有权
标题翻译：具有本地和全局设备的存储器件在与堆叠层的存储器单元和方法基本相同的水平上
公开(公告)号：US09070442B2
公开(公告)日：2015-06-30
申请号：US14013370
申请日：2013-08-29
申请人： Micron Technology, Inc.
发明人： Aaron S. Yip , Mark A. Helm , Ramin Ghodsi
IPC分类号： G11C16/00 , G11C16/02 , G11C11/063 , G11C11/06 , G11C5/02
CPC分类号： G11C5/025 , G11C5/063 , G11C8/08 , G11C11/06035 , G11C11/06064 , G11C11/063 , G11C16/02 , G11C16/0483 , H01L27/11531 , H01L27/11573 , Y10T29/49069
摘要： In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
摘要翻译：在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层。本地设备可以提供对数据线的选择性访问。全局设备可以提供对全局接入线的选择性访问。一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

5. 发明授权

US07936584B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US07936584B2
公开(公告)日：2011-05-03
申请号：US12354425
申请日：2009-01-15
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/06
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

6. 发明申请

US20090040855A1 METHOD AND SYSTEM FOR PROVIDING A SENSE AMPLIFIER AND DRIVE CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权
标题翻译：用于提供感测放大器和驱动电路的方法和系统，用于旋转转矩磁性随机存取存储器
公开(公告)号：US20090040855A1
公开(公告)日：2009-02-12
申请号：US11834917
申请日：2007-08-07
申请人： Xiao Luo , David Chang-Cheng Yu
发明人： Xiao Luo , David Chang-Cheng Yu
IPC分类号： G11C7/00 , G11C11/06
CPC分类号： G11C11/1673 , G11C11/1659
摘要： A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.
摘要翻译：描述了一种用于提供磁存储器的方法和系统。该方法和系统包括多个磁存储单元，多个位线，至少一个参考线和至少一个读出放大器。每个磁存储单元包括磁性元件和选择装置。磁性元件可通过驱动通过磁性元件的写入电流来编程。位线和源极线对应于磁存储单元。读出放大器与位线和参考线耦合，并且包括逻辑和多个级。阶段包括第一和第二阶段。第一级至少将电流信号转换为至少一个差分电压信号。第二级放大至少一个差分电压信号。在没有读取操作的情况下，逻辑选择性地抵消第一级和第二级中的至少一级，并且在读取操作期间启用第一级和第二级。

7. 发明授权

US07414908B2 Magnetic memory device 有权
标题翻译：磁存储器件
公开(公告)号：US07414908B2
公开(公告)日：2008-08-19
申请号：US11000486
申请日：2004-11-30
申请人： Hisatada Miyatake , Toshio Sunaga
发明人： Hisatada Miyatake , Toshio Sunaga
IPC分类号： G11C7/02 , G11C11/06 , G11C5/08 , G11C5/14
CPC分类号： G11C11/16 , G11C7/062 , G11C14/0081
摘要： A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding pairs of bit lines at high speed. This is accomplished by a sense amplifier including CMOS inverters cross-connected or connected in loop, a P-channel MOS transistor for shutting the power off during standby, and N-channel MOS transistors for initializing the output of the sense amplifier during standby. A ground terminal of the inverter is connected to a bit line through a transistor of a bit switch, and a ground terminal of the inverter is connected to a bit line through a transistor of a bit switch.
摘要翻译：磁性随机存取存储器（MRAM）其中通过MTJ元件流过很少的电流并且在其上施加非常小的电压，MRAM被提供有能够放大其相应的高位位线之间的电位差的读出放大器速度。这是通过包括交叉连接或环路连接的CMOS反相器的感测放大器，用于在待机期间关闭电源的P沟道MOS晶体管和用于在待机期间初始化读出放大器的输出的N沟道MOS晶体管实现的。逆变器的接地端子通过位开关的晶体管连接到位线，并且反相器的接地端子通过位开关的晶体管连接到位线。

8. 发明授权

US07190604B2 Capacity dividable memory IC 有权
标题翻译：容量分配存储器IC
公开(公告)号：US07190604B2
公开(公告)日：2007-03-13
申请号：US11166586
申请日：2005-06-27
申请人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
发明人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
IPC分类号： G11C5/06 , G11C8/00 , G11C11/06
CPC分类号： G11C5/06
摘要： Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.
摘要翻译：晶片上的两个存储区域通过传输晶体管耦合以使每个区域的存储器容量加倍，并且可以锯切以产生两个具有单个存储器区域的存储器芯片。当传输晶体管导通时，一对传输晶体管用于将两个存储区域中的每个专用功能焊盘耦合。传输晶体管对之间的连接可以被锯切以产生单容量存储器芯片。通过将更多的存储区域与传输晶体管连接可以进一步增加存储器容量。

9. 发明申请

US20070030718A1 Magnetic logic system 审中-公开
标题翻译：磁逻辑系统
公开(公告)号：US20070030718A1
公开(公告)日：2007-02-08
申请号：US10547141
申请日：2004-02-27
申请人： Russell Cowburn
发明人： Russell Cowburn
IPC分类号： G11C11/06
CPC分类号： G11C19/0841 , G11C19/0808 , H03K19/16
摘要： A driving system and method to effect propagation of a magnetic domain wall through a ferromagnetic conduit are described, wherein oscillating electrical current is passed through the conduit from an oscillating current supply source via at least two electrical contacts adapted to make electrical connection with at least two spaced points on the conduit. A ferromagnetic conduit is described comprising an elongate ferromagnetic element formed as a continuous track of magnetic material capable of sustaining and propagating a domain wall, and such a driving system in serial array, preferably being further adapted to serve as a magnetic logic element by the provision of nodes and/or directional changes as a result of which logical functions may be processed.
摘要翻译：描述了通过铁磁导管传播磁畴壁的驱动系统和方法，其中振荡电流通过至少两个电接触器从振荡电流源供应源穿过导管，适于与至少两个电气连接导管上的间隔点。描述了一种铁磁导管，其包括形成为能够维持和传播畴壁的磁性材料的连续轨道的细长铁磁元件，以及串联阵列的这种驱动系统，优选地进一步适于通过所述设置用作磁逻辑元件的节点和/或方向改变，由此可以处理逻辑功能。

10. 发明授权

US07116606B2 Method and circuit of plasma damage protection 有权
标题翻译：等离子体损伤保护的方法和电路
公开(公告)号：US07116606B2
公开(公告)日：2006-10-03
申请号：US11034945
申请日：2005-01-14
申请人： Ming-Hung Chou , Wen-Pin Lu
发明人： Ming-Hung Chou , Wen-Pin Lu
IPC分类号： G11C11/06
CPC分类号： H01L27/0266
摘要： A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.
摘要翻译：用于在半导体器件或集成电路中放电等离子体感应电荷的保护电路包括PMOS晶体管和二极管。 PMOS晶体管包括衬底，漏极，源极和栅极，源极被耦合以接收等离子体感应的电荷。二极管具有耦合到PMOS晶体管的衬底的正极端子和耦合PMOS晶体管的栅极的负极端子。

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