专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170179954A1 LOW POWER CONSUMPTION LOGIC CELL 有权
公开(公告)号：US20170179954A1
公开(公告)日：2017-06-22
申请号：US15381477
申请日：2016-12-16
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Hervé Fanet , Samer Houri , Gaël Pillonnet
IPC分类号： H03K19/00 , H03K19/185
CPC分类号： H03K19/0008 , H03K19/0013 , H03K19/0019 , H03K19/02 , H03K19/185 , H03K19/20
摘要： The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.

2. 发明授权

US09576094B2 Logic circuit and system and computer program product for logic synthesis 有权
标题翻译：用于逻辑综合的逻辑电路和系统及计算机程序产品
公开(公告)号：US09576094B2
公开(公告)日：2017-02-21
申请号：US14464366
申请日：2014-08-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , NATIONAL TAIWAN UNIVERSITY
发明人： Chi-Chuan Chuang , Yi-Hsiang Lai , Jie-Hong Chiang
IPC分类号： G06F17/50 , H03K19/00 , H03K19/04 , H03K19/096 , H03K19/02
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5031 , G06F17/504 , G06F17/5045 , G06F17/5054 , G06F17/5059 , G06F2217/06 , G06F2217/84 , H03K19/00 , H03K19/02 , H03K19/04 , H03K19/0948 , H03K19/0966
摘要： A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.
摘要翻译：逻辑电路包括第一和第二输入，输出，输入确认节点，输出确认节点，逻辑评估块，预充电电路和完成检测电路。逻辑评估块在第一和第二输入端执行第一和第二输入信号的逻辑评估，并输出对应于逻辑评估的输出信号。预充电电路响应于输入确认节点处的第一输入信号和确认信号，对逻辑评估块进行预充电。完成检测电路响应于第二输入信号和输出信号在输出确认节点产生确认信号。

3. 发明授权

US09548741B1 Memristive akers logic array 有权
标题翻译： Memristive akers逻辑阵列
公开(公告)号：US09548741B1
公开(公告)日：2017-01-17
申请号：US14798485
申请日：2015-07-14
申请人： Technion Research and Development Foundation LTD.
发明人： Shahar Kvatinsky , Avinoam Kolodny , Yifat Hanein
IPC分类号： H03K19/173 , H03K19/177 , H03K19/02 , H03K19/094
CPC分类号： H03K19/1776 , G11C13/0007 , H03K19/02 , H03K19/094 , H03K19/17708
摘要： A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.
摘要翻译：一种包括忆阻阿克斯逻辑阵列的装置，其中忆阻Akers逻辑阵列包括彼此耦合的多个基本逻辑单元; 其中每个基元逻辑单元包括至少一个忆阻器件。

4. 发明授权

US09501600B2 Standard cells for predetermined function having different types of layout 有权
标题翻译：用于具有不同类型布局的预定功能的标准单元
公开(公告)号：US09501600B2
公开(公告)日：2016-11-22
申请号：US14051881
申请日：2013-10-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
IPC分类号： G06F17/50 , H03K19/02 , H01L27/02
CPC分类号： G06F17/5072 , G06F17/5068 , H01L27/0207 , H03K19/02
摘要： An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
摘要翻译：通过具有金属线的标称最小间距的预定制造工艺制造集成电路。集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。

5. 发明申请

US20160226491A1 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
标题翻译：用于促进可编程逻辑电路与具有时钟调整的应用特定集成电路之间的通信的方法和装置
公开(公告)号：US20160226491A1
公开(公告)日：2016-08-04
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/02
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
摘要翻译：公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

6. 发明授权

US09276579B2 Nano-electro-mechanical-switch adiabatic dynamic logic circuits 有权
标题翻译：纳米机电开关绝热动态逻辑电路
公开(公告)号：US09276579B2
公开(公告)日：2016-03-01
申请号：US14036185
申请日：2013-09-25
申请人： International Business Machines Corporation
发明人： Michel Despont , Daniel Grogg , Christoph Hagleitner , Yu Pu
IPC分类号： H03K19/02 , H03K19/20
CPC分类号： H03K19/02 , H03K19/20
摘要： A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.
摘要翻译：动态逻辑门包括纳米机电开关，优选四端子纳米机电开关。本发明还涉及包括这种动态逻辑门的动态逻辑级联电路。特别地，本发明的实施例涉及包括单轨或双轨动态逻辑门的动态逻辑级联电路。

7. 发明授权

US09276564B1 Noise-assisted reprogrammable nanomechanical logic gate and method 有权
公开(公告)号：US09276564B1
公开(公告)日：2016-03-01
申请号：US13886977
申请日：2013-05-03
申请人： The United States of America as represented by the Secretary of the Navy
发明人： William L. Ditto , Pritiraj Mohanty , Sudeshna Sinha , Ardeshir R. Bulsara , Diego Guerra , Krishnamurthy Murali
IPC分类号： H03K19/195 , H03K3/013 , H03K19/20 , B82Y99/00
CPC分类号： H03K3/013 , B82Y99/00 , H03K19/02 , H03K19/20
摘要： A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.

8. 发明授权

US08872542B2 Semiconductor device and semiconductor device control method 有权
标题翻译：半导体器件和半导体器件控制方法
公开(公告)号：US08872542B2
公开(公告)日：2014-10-28
申请号：US13825243
申请日：2011-09-21
申请人： Noboru Sakimura , Munehiro Tada , Toshitsugu Sakamoto , Ryusuke Nebashi
发明人： Noboru Sakimura , Munehiro Tada , Toshitsugu Sakamoto , Ryusuke Nebashi
IPC分类号： H03K19/177 , G11C13/00 , H03K19/02 , G11C29/02
CPC分类号： H03K19/17748 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0073 , H03K19/02
摘要： A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit.
摘要翻译：一种半导体器件包括：可重构逻辑电路，包括多个电阻变化元件; 可重新配置逻辑电路的逻辑配置根据多个电阻变化元件中的每一个是处于第一电阻状态还是在电阻值低于第一电阻状态的电阻值的第二电阻状态决定; 电阻值监视电路，包括预编程到第一电阻状态的电阻变化元件; 检测预编程电阻变化元件是否保持第一电阻状态的电阻值监视电路; 以及控制器，在检测到电阻值监视电路中设置的电阻变化元件未保持第一电阻状态的情况下，将从第二电阻状态到第一电阻状态的编程中使用的电压施加到保持第一电阻状态的电阻变化元件，设置在可重构逻辑电路中的多个电阻变化元件。

9. 发明申请

US20140021982A1 NANOELECTROMECHANICAL LOGIC DEVICES 有权
标题翻译：纳米电子逻辑器件
公开(公告)号：US20140021982A1
公开(公告)日：2014-01-23
申请号：US12987804
申请日：2011-01-10
申请人： Massood Tabib-Azar
发明人： Massood Tabib-Azar
IPC分类号： H03K19/02 , H01L21/28
CPC分类号： B81C1/00142 , H01H1/0094 , H01H1/20 , H01H59/0009 , H01L21/28 , H03K19/02
摘要： Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the bridges. The logic electrodes can provide logical functions of the applied voltages.
摘要翻译：纳米机电逻辑器件可以包括具有控制和逻辑电极的多个柔性桥。施加到控制电极的电压可用于控制桥的弯曲。逻辑电极可提供施加电压的逻辑功能。

10. 发明申请

US20130181739A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE CONTROL METHOD 有权
标题翻译：半导体器件和半导体器件控制方法
公开(公告)号：US20130181739A1
公开(公告)日：2013-07-18
申请号：US13825243
申请日：2011-09-21
申请人： Noboru Sakimura , Munehiro Tada , Toshitsugu Sakamoto , Ryusuke Nebashi
发明人： Noboru Sakimura , Munehiro Tada , Toshitsugu Sakamoto , Ryusuke Nebashi
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0073 , H03K19/02
摘要： A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit.
摘要翻译：一种半导体器件包括：包括多个电阻变化元件的可重构逻辑电路; 可重新配置逻辑电路的逻辑配置根据多个电阻变化元件中的每一个是处于第一电阻状态还是在电阻值低于第一电阻状态的电阻值的第二电阻状态决定; 电阻值监视电路，包括预编程到第一电阻状态的电阻变化元件; 检测预编程电阻变化元件是否保持第一电阻状态的电阻值监视电路; 以及控制器，在检测到电阻值监视电路中设置的电阻变化元件未保持第一电阻状态的情况下，将从第二电阻状态到第一电阻状态的编程中使用的电压施加到保持第一电阻状态的电阻变化元件，设置在可重构逻辑电路中的多个电阻变化元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式