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51. 发明授权

US08964826B2 Time domain analog multiplication techniques for adjusting tap weights of feed-forward equalizers 有权
标题翻译：用于调整前馈均衡器的抽头权重的时域模拟乘法技术
公开(公告)号：US08964826B2
公开(公告)日：2015-02-24
申请号：US13763659
申请日：2013-02-09
申请人： International Business Machines Corporation
发明人： Ankur Agrawal , John F. Bulzacchelli
IPC分类号： H03H7/30 , H04L25/03 , H04L27/01 , H03K5/135 , H03K5/00
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to a given FFE tap during the integration period to enable the given FFE tap during a portion of the integration period in which the gating control signal overlaps the integration period so as to effectively multiply the data signal input to the given FFE tap with an FFE coefficient value corresponding to a period of overlap between the gating control signal and the integration period.
摘要翻译：提供前馈均衡器（FFE）电路和方法，其实现时域模拟乘法以调整FFE抽头权重。例如，一种方法包括将数据信号输入到电流积分加法电路的FFE抽头，其中数据信号是模拟输入数据信号的时间延迟版本。在电流积分夏季电路的复位期间，将电容充电至预充电电平。在积分积分电路的积分期间，由每个FFE抽头产生输出电流。来自FFE抽头的输出电流在积分期间共同对电容进行充电或放电。在积分周期期间，门控控制信号被施加到给定的FFE抽头，以便在选通控制信号与积分周期重叠的积分周期的一部分期间实现给定的FFE抽头，以便有效地将输入的数据信号乘以给定的 FFE抽头具有对应于门控控制信号和积分周期之间的重叠周期的FFE系数值。

52. 发明授权

US08964825B2 Analog signal current integrators with tunable peaking function 有权
标题翻译：具有可调谐峰值功能的模拟信号电流积分器
公开(公告)号：US08964825B2
公开(公告)日：2015-02-24
申请号：US13399675
申请日：2012-02-17
申请人： Troy J. Beukema , John F. Bulzacchelli
发明人： Troy J. Beukema , John F. Bulzacchelli
IPC分类号： H03H7/30 , H04B1/10
CPC分类号： G06G7/184 , H03F3/45098 , H03F2203/45296 , H03F2203/45298 , H03F2203/45374 , H03F2203/45466 , H03F2203/45616 , H03F2203/45618 , H04L25/0296 , H04L25/03885
摘要： Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
摘要翻译：模拟信号电流积分器具有可调峰值功能。具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿，适用于包含高级均衡功能的高数据速率接收机集成电路中的应用，如决策反馈均衡器。例如，电流积分器电路包括电流积分放大器电路，该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应，以及峰化控制电路，用于产生控制信号，以将可调节电路元件的值调整为当前积分器电路的工作状态的功能。操作条件可以是指定的数据速率或通信信道特性，也可以是两者。可调电路元件可以是退化电容器或偏置电流源。

53. 发明授权

US08942281B2 Method for processing signals 有权
标题翻译：处理信号的方法
公开(公告)号：US08942281B2
公开(公告)日：2015-01-27
申请号：US13450954
申请日：2012-04-19
申请人： Dirk Daecke
发明人： Dirk Daecke
IPC分类号： H03H7/30 , H04B3/14 , H04L25/03
CPC分类号： H04B3/14 , H04L25/03878
摘要： A method for processing signals transmitted via a connection and received by a digital interface, where individual data frames are transmitted by the signals as a sequence of modulated symbols, and where the received signals are corrected by an equalizer; the equalizer sampling the received signals, and an adaptation of the equalizer only taking place in particular time intervals in a manner controlled by a protocol.
摘要翻译：一种处理经由连接发送并由数字接口接收的信号的方法，其中各个数据帧由信号作为调制符号序列发送，并且其中接收信号由均衡器校正; 均衡器对接收到的信号进行采样，并且均衡器的调整仅以特定时间间隔以由协议控制的方式发生。

54. 发明授权

US08937994B2 Partial response decision feedback equalizer with selection circuitry having hold state 有权
标题翻译：具有保持状态的选择电路的部分响应判决反馈均衡器
公开(公告)号：US08937994B2
公开(公告)日：2015-01-20
申请号：US13915290
申请日：2013-06-11
申请人： Rambus Inc.
发明人： Amir Amirkhany , Kambiz Kaviani , Aliazam Abbasfar
IPC分类号： H03H7/30 , H03K5/24
CPC分类号： H04L25/03949 , H03K5/24
摘要： A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.
摘要翻译：部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择产生相应的第一和第二选择输出。第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。选择信号取决于序列中第一个已解析符号之前的先前解析符号。

55. 发明授权

US08934525B2 High-speed signaling systems and methods with adaptable, continuous-time equalization 有权
标题翻译：具有适应性，连续时间均衡的高速信号系统和方法
公开(公告)号：US08934525B2
公开(公告)日：2015-01-13
申请号：US12522362
申请日：2008-01-07
申请人： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
发明人： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03
CPC分类号： H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
摘要： A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
摘要翻译：接收机包括连续时间均衡器，判决反馈均衡器（DFE），数据和误差采样逻辑以及适配引擎。接收机通过基于第一后视标ISI的测量建立连续时间均衡器的适当均衡设置来校正与最新数据符号（第一后光标ISI）相关联的符号间干扰（ISI）。

56. 发明授权

US08923416B2 Symbol-level repetition coding in power line communications 有权
标题翻译：电力线通信中的符号级重复编码
公开(公告)号：US08923416B2
公开(公告)日：2014-12-30
申请号：US13267300
申请日：2011-10-06
申请人： Il Han Kim , Badri N. Varadarajan , Anand G. Dabak
发明人： Il Han Kim , Badri N. Varadarajan , Anand G. Dabak
IPC分类号： H04B3/00 , H03H7/30 , H04W4/00 , H04B3/54 , H04L1/08 , H04L1/00
CPC分类号： H04L1/08 , H04B3/54 , H04B3/546 , H04B2203/5408 , H04B2203/5425 , H04B2203/5433 , H04B2203/5466 , H04L1/0059 , H04L1/0065
摘要： Systems and methods for implementing symbol-level repetition coding in power line communications (PLC) are described. In some embodiments, these systems and methods may provide reliable communication in severe channel environments of PLC networks, at least in part, by changing the forward error correction (FEC) used by various devices operating within current PLC systems. For example, a method may include receiving a PLC signal and applying convolutional encoding to the received signal, the convolutional encoding producing an encoded signal. The method may also include performing a subcarrier modulation operation upon the encoded signal, the subcarrier modulation operation producing a modulated signal. The method may further include applying symbol-level repetition coding to the modulated signal, the symbol-level repetition coding producing a repetitious signal. In some cases, one or more distinct repetition patterns may be applied to different symbols or portions thereof. The repetitious signal may then be transmitted over a power line.
摘要翻译：描述了在电力线通信（PLC）中实现符号级重复编码的系统和方法。在一些实施例中，这些系统和方法可以至少部分地通过改变在当前PLC系统中操作的各种设备使用的前向纠错（FEC）来在PLC网络的严酷信道环境中提供可靠的通信。例如，一种方法可以包括接收PLC信号并对接收到的信号应用卷积编码，卷积编码产生编码信号。该方法还可以包括对编码信号执行子载波调制操作，产生调制信号的子载波调制操作。该方法还可以包括对调制信号应用符号级重复编码，产生符号级重复编码产生重复信号。在一些情况下，可以将一个或多个不同的重复图案应用于不同的符号或其部分。然后可以通过电力线传输重复信号。

57. 发明授权

US08913653B2 Efficient equalizer coefficient computation 有权
标题翻译：高效均衡器系数计算
公开(公告)号：US08913653B2
公开(公告)日：2014-12-16
申请号：US13622911
申请日：2012-09-19
申请人： Nvidia Corporation
发明人： Vishwambhar Rathi , Carlo Luschi
IPC分类号： H03H7/30 , H04L27/01
CPC分类号： H04L25/03044 , H04L2025/03592
摘要： An equalization parameter analyzer includes a parameter section configured to acquire at least one current parameter for a wireless receiver and an analyzer section configured to compare the at least one current parameter with at least one corresponding previous parameter. Additionally, the equalization parameter analyzer also includes a coefficients section configured to initiate a generation of new equalizer coefficients in the wireless receiver based on a change between the at least one current and corresponding previous parameters that exceeds a predefined threshold. A method of equalization coefficients generation is also provided.
摘要翻译：均衡参数分析器包括被配置为获取无线接收器的至少一个当前参数的参数部分和被配置为将至少一个当前参数与至少一个对应的先前参数进行比较的分析器部分。另外，均衡参数分析器还包括系数部分，其被配置为基于超过预定义阈值的至少一个当前和相应的先前参数之间的变化来在无线接收器中发起新的均衡器系数的产生。还提供了均衡系数产生的方法。

58. 发明授权

US08902964B2 Equalization effort-balancing of transmit finite impulse response and receive linear equalizer or receive decision feedback equalizer structures in high-speed serial interconnects 有权
标题翻译：平衡发射有限脉冲响应和接收线性均衡器或接收高速串行互连中的判决反馈均衡器结构
公开(公告)号：US08902964B2
公开(公告)日：2014-12-02
申请号：US13631877
申请日：2012-09-29
申请人： Intel Corporation
发明人： Manuel A. Aguilar-Arreola , Eric J. Msechu
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L27/01
CPC分类号： H04L25/03878 , H04L25/03343 , H04L25/14 , H04L27/01 , H04L2025/03433 , H04L2025/03535
摘要： Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.
摘要翻译：描述了在高速串行互连中提供发射（TX）有限脉冲响应（FIR）和接收（RX）线性均衡器（LE）或RX判决反馈均衡器（DFE）结构的均衡均衡的方法和装置。在一些实施例中，检测对应于具有多个通道的链路的每个通道的多个发送均衡值和多个接收均衡值的数据。基于在判决反馈均衡器（DFE）抽头中的饱和度的检测，多个发送均衡值中的至少一个和多个接收均衡值中的至少一个被选择为链路的多个通道中的每个通道的链接的相应通道。还要求和/或公开其它实施例。

59. 发明授权

US08879616B2 Receiver with decision feedback equalizer 有权
标题翻译：具有判决反馈均衡器的接收器
公开(公告)号：US08879616B2
公开(公告)日：2014-11-04
申请号：US13285195
申请日：2011-10-31
申请人： Dacheng Zhou , Daniel Alan Berkram
发明人： Dacheng Zhou , Daniel Alan Berkram
IPC分类号： H03H7/30 , H04L25/03
CPC分类号： H04L25/03063 , H04L25/03248
摘要： A receiver includes a front-end amplifier, a sampler, and a decision-feedback equalizer. The front-end amplifier provides for amplifying a received input signal to yield an amplified input signal. The sampler provides for sampling the amplified input signal so as to yield a sampler output signal. The sampler output signal is a function of the amplified input signal and a reference signal coupled to a reference input of the sampler. The decision feedback equalizer provides for adjusting the reference signal as a function of feedback based at least in part on the sampler output signal.
摘要翻译：接收机包括前端放大器，采样器和判决反馈均衡器。前端放大器用于放大接收的输入信号以产生放大的输入信号。采样器提供对放大的输入信号进行采样，以产生采样器输出信号。采样器输出信号是放大的输入信号和耦合到采样器的参考输入的参考信号的函数。决策反馈均衡器至少部分地基于采样器输出信号，提供作为反馈的函数的参考信号的调整。

60. 发明授权

US08867598B1 Timing and data recovery in feed-forward equalization 有权
标题翻译：前馈均衡的时序和数据恢复
公开(公告)号：US08867598B1
公开(公告)日：2014-10-21
申请号：US13585409
申请日：2012-08-14
申请人： Mathieu Gagnon
发明人： Mathieu Gagnon
IPC分类号： H03K5/159 , H03H7/30 , H03H7/40
CPC分类号： H04L25/03031 , H04L7/0087 , H04L7/033
摘要： An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.
摘要翻译：公开了一种均衡器及其相关操作方法。均衡器具有通过获得与未来和过去发送的比特强烈相关的样本来平衡性能和复杂度的配置，并且与未来和过去的比特转换弱相关，并且对于定时恢复电路是有用的。样品只能以比参考样品多于一个样品周期的时间间隔获得或收集。样本移动小于采样周期的延迟值，并且以一个单位间隔的采样周期获得。还公开了一种调整采样点延迟的方法。在实现中，获取远离参考样本的采样周期内的采样，并用于实现定时偏移，而不是用于定时恢复信号的均衡。还公开了用于优化用于数据恢复的性能的实施例。

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