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1. 发明申请

US20160013955A1 On-Chip AC Coupled Receiver with Real-Time Linear Baseline-Wander Compensation 有权
标题翻译：具有实时线性基线漂移补偿的片上AC耦合接收器
公开(公告)号：US20160013955A1
公开(公告)日：2016-01-14
申请号：US14789794
申请日：2015-07-01
申请人： Rambus Inc.
发明人： Yikui Jen Dong
IPC分类号： H04L25/03 , H04L25/06
CPC分类号： H04L25/03019 , H03K5/007 , H04L25/0292 , H04L25/0296 , H04L25/06 , H04L47/50
摘要： An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.
摘要翻译：具有基线漂移补偿的片上AC耦合接收器。接收机可以用于单端或差分信号。接收机包括用于接收输入信号的输入端。 AC耦合电路位于输入端和节点之间，并将输入信号耦合到节点处的耦合信号。控制回路感测节点处的低频信号内容，并且基于低频信号内容使用线性缓冲器来调整节点处的耦合信号。控制环路的操作补偿了耦合信号中潜在的基线漂移。用于从节点处的耦合信号恢复数据的输入级。

2. 发明申请

US20140146922A1 QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES 有权
标题翻译： QUASI-DIGITAL接收器用于高速伺服系统
公开(公告)号：US20140146922A1
公开(公告)日：2014-05-29
申请号：US13720623
申请日：2012-12-19
申请人： BROADCOM CORPORATION
发明人： Ali Nazemi , Mahmoud Reza Ahmadi , Tamer Ali , Bo Zhang , Mohammed Abdul-Latif , Namik Kocaman , Afshin Momtaz
IPC分类号： H04L25/02
CPC分类号： H04L7/00 , H04L7/002 , H04L25/0272 , H04L25/0292 , H04L25/0296 , H04L25/06
摘要： Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.
摘要翻译：这里描述了提供用于接收和反序列化数字比特流的接口的技术。例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。数字限幅器可以被配置为确定数据输入的数字值。数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

3. 发明授权

US08634452B2 Multiphase receiver with equalization circuitry 有权
标题翻译：具有均衡电路的多相接收器
公开(公告)号：US08634452B2
公开(公告)日：2014-01-21
申请号：US13491508
申请日：2012-06-07
申请人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号： H04B17/00
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译：集成电路装置包括：第一电路，用于接收与电输入信号的第一数据周期相关联的位，可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路，用于接收与第电输入信号的第二周期，以产生关于与第二数据周期相关联的位的逻辑状态的判定。均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰，并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰，该电路可操作以产生关于位的逻辑状态的判定的电气输入信号。

4. 发明申请

US20130215954A1 ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION 有权
标题翻译：具有可调峰值功能的模拟信号电流积分器
公开(公告)号：US20130215954A1
公开(公告)日：2013-08-22
申请号：US13399675
申请日：2012-02-17
申请人： Troy J. Beukema , John F. Bulzacchelli
发明人： Troy J. Beukema , John F. Bulzacchelli
IPC分类号： H04L27/01 , H03F3/45
CPC分类号： G06G7/184 , H03F3/45098 , H03F2203/45296 , H03F2203/45298 , H03F2203/45374 , H03F2203/45466 , H03F2203/45616 , H03F2203/45618 , H04L25/0296 , H04L25/03885
摘要： Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
摘要翻译：模拟信号电流积分器具有可调峰值功能。具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿，适用于包含高级均衡功能的高数据速率接收机集成电路中的应用，如决策反馈均衡器。例如，电流积分器电路包括电流积分放大器电路，该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应，以及峰值控制电路，用于产生控制信号，以将可调节电路元件的值调整为当前积分器电路的工作状态的功能。操作条件可以是指定的数据速率或通信信道特性，也可以是两者。可调电路元件可以是退化电容器或偏置电流源。

5. 发明申请

US20110028104A1 RECEIVER FOR SIGNAL COMMUNICATION SYSTEM WITH DISTURBANCE REJECTION CIRCUIT 有权
标题翻译：具有干扰抑制电路的信号通信系统接收机
公开(公告)号：US20110028104A1
公开(公告)日：2011-02-03
申请号：US12846565
申请日：2010-07-29
申请人： Salvatore Giombanco , Michele Grande , Giovanni Lombardo , Salvatore Tumminaro , Filippo Marino
发明人： Salvatore Giombanco , Michele Grande , Giovanni Lombardo , Salvatore Tumminaro , Filippo Marino
IPC分类号： H04B1/40
CPC分类号： H04L25/0266 , H04L25/0276 , H04L25/0296
摘要： A receiver of a signal communication apparatus; the apparatus having a transmitter for transmitting the signals, the receiver for receiving the signals and a galvanically isolated wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver including a disturbance rejection circuit coupled to the receiving antenna and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.
摘要翻译：信号通信装置的接收机; 所述装置具有用于发送信号的发射机，用于接收信号的接收机和插在发射机和接收机之间并且具有发射天线和接收天线的电隔离无线接口。接收机包括耦合到接收天线的干扰抑制电路，并且能够以电隔离接口的输入和输出之间的电势变化来补偿在发射天线和接收天线之间流动的寄生电流。

6. 发明申请

US20110026612A1 RECEIVER FOR SIGNAL COMMUNICATION APPARATUS AND RELATED SIGNAL COMMUNICATION APPARATUS 有权
标题翻译：信号通信装置和相关信号通信装置的接收机
公开(公告)号：US20110026612A1
公开(公告)日：2011-02-03
申请号：US12846508
申请日：2010-07-29
申请人： Giovanni Lombardo , Salvatore Giombanco , Michele Grande , Salvatore Tumminaro , Filippo Marino
发明人： Giovanni Lombardo , Salvatore Giombanco , Michele Grande , Salvatore Tumminaro , Filippo Marino
IPC分类号： H04L25/00 , H04L27/00
CPC分类号： H04L25/0266 , H04L25/0276 , H04L25/0296
摘要： A receiver of a signal communication apparatus; the apparatus including a transmitter adapted to transmit coded signals, the receiver for receiving the signal and a wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver includes a decoder configured to decode the received signal and circuitry coupled to the receiving antenna and capable of triggering the decoder if the value of the received signal is outside a logical hysteresis having a first logic threshold having a value smaller than the value of the direct current component of the received signal and a second logic threshold having a value greater than the value of the direct current component of the received signal.
摘要翻译：信号通信装置的接收机; 所述装置包括适于发送编码信号的发射机，用于接收信号的接收机和插在发射机和接收机之间并具有发射天线和接收天线的无线接口。接收机包括解码器，其被配置为对接收到的信号进行解码并耦合到接收天线，并且能够触发解码器，如果接收信号的值在逻辑滞后之外，该逻辑迟滞的第一逻辑阈值的值小于接收信号的直流分量和具有大于接收信号的直流分量的值的第二逻辑阈值。

7. 发明授权

US07869777B2 Method and system for a second order input intercept point (IIP2) correction 有权
标题翻译：二阶输入截点（IIP2）校正方法和系统
公开(公告)号：US07869777B2
公开(公告)日：2011-01-11
申请号：US12200660
申请日：2008-08-28
申请人： Hooman Darabi
发明人： Hooman Darabi
IPC分类号： G06F3/033
CPC分类号： H04L25/061 , H03D3/008 , H04B1/30 , H04L25/0272 , H04L25/0294 , H04L25/0296
摘要： In RF transceivers, a method and system for a second order input intercept point (IIP2) correction are provided. A DC offset sensor may detect DC offset voltages produced by blocker signals in “I” and “Q” signal component paths in an RF receiver. The DC offset sensor may generate control signals which may be utilized by a first and second injection circuits to generate DC offset currents that compensate for the DC offset voltages in the signal component paths. An injection circuit may utilize current drivers to generate binary weighted currents which may be added together to produce a DC offset current. The polarity of the DC offset current and the selection of which current drivers to use may be determined by the control signals. A calibration voltage may also be utilized to correct or adjust the gain in the injection circuit.
摘要翻译：在RF收发器中，提供了用于二阶输入截点（IIP2）校正的方法和系统。 DC偏移传感器可以检测RF接收机中的“I”和“Q”信号分量路径中的阻塞信号产生的DC偏移电压。 DC偏移传感器可以产生可由第一和第二注入电路利用的控制信号，以产生补偿信号分量路径中的DC偏移电压的DC偏移电流。注入电路可以利用电流驱动器来产生可加在一起以产生DC偏移电流的二进制加权电流。 DC偏移电流的极性和使用哪些电流驱动器的选择可以由控制信号确定。也可以使用校准电压来校正或调整注入电路中的增益。

8. 发明授权

US07864183B1 Dynamic switching of memory termination characteristics in a graphics system 有权
标题翻译：图形系统中存储器终端特性的动态切换
公开(公告)号：US07864183B1
公开(公告)日：2011-01-04
申请号：US11683957
申请日：2007-03-08
申请人： Bruce Lam , Luc Bisson , Gabriele Gorla , Tom Dewey , Andrew Bell
发明人： Bruce Lam , Luc Bisson , Gabriele Gorla , Tom Dewey , Andrew Bell
IPC分类号： G06F13/14 , H03K17/16 , G11C7/00
CPC分类号： G09G5/39 , G09G2330/021 , G11C7/1048 , H04L25/0296 , H04L25/0298
摘要： A graphics system includes a graphics memory. The graphics system includes a high performance mode and at least one power savings mode. A termination impedance and switching threshold of the graphics memory are selected based on an operating mode of the graphics system.
摘要翻译：图形系统包括图形存储器。图形系统包括高性能模式和至少一个省电模式。基于图形系统的操作模式来选择图形存储器的终止阻抗和切换阈值。

9. 发明授权

US07706309B2 Data transfer control device, electronic instrument, and data transfer control method 失效
标题翻译：数据传输控制装置，电子仪器和数据传输控制方法
公开(公告)号：US07706309B2
公开(公告)日：2010-04-27
申请号：US11073857
申请日：2005-03-08
申请人： Yukinari Shibata , Tomonaga Hasegawa
发明人： Yukinari Shibata , Tomonaga Hasegawa
IPC分类号： H04B1/44 , H04B1/56
CPC分类号： H04L25/4908 , H04L5/1438 , H04L5/16 , H04L5/18 , H04L25/0274 , H04L25/0284 , H04L25/0296
摘要： A data transfer control device includes: a transmitter circuit; a receiver circuit; a transfer direction switch circuit which performs switching a transfer direction; a transfer direction switch indication circuit which indicates the transfer direction switch circuit to switch the transfer direction; and a code generation circuit which generates a transfer direction switch request code when a transfer direction switch request has been received from an upper layer circuit. When the transfer direction switch request has been received from the upper layer circuit, the transmitter circuit transmits the transfer direction switch request code through a serial signal line, and the transfer direction switch indication circuit indicates the transfer direction switch circuit to switch from a transmission direction to a reception direction after the transfer direction switch request code has been transmitted.
摘要翻译：数据传输控制装置包括：发射机电路; 接收机电路; 执行切换传送方向的传送方向切换电路; 传送方向切换指示电路，其指示传送方向切换电路切换传送方向; 以及代码生成电路，当从上层电路接收到传送方向切换请求时，生成传送方向切换请求代码。当从上层电路接收到传送方向切换请求时，发送电路通过串行信号线发送传送方向切换请求码，传送方向切换指示电路表示传送方向切换电路从传送方向切换在传送方向切换请求代码已经被发送之后到接收方向。

10. 发明授权

US07532046B2 Receiver for a differential data bus 有权
标题翻译：接收器用于差分数据总线
公开(公告)号：US07532046B2
公开(公告)日：2009-05-12
申请号：US11632031
申请日：2005-06-30
申请人： Jelle Nico Wolthek , Cornelis Klaas Waardenburg , Cecilius Gerardus Kwakernaat , Stefan Gerhard Erich Butselaar
发明人： Jelle Nico Wolthek , Cornelis Klaas Waardenburg , Cecilius Gerardus Kwakernaat , Stefan Gerhard Erich Butselaar
IPC分类号： H03B1/00
CPC分类号： H04L25/0296 , H03F3/45991 , H03F2203/45538 , H03F2203/45588 , H03F2203/45616 , H04L25/0274
摘要： The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.
摘要翻译：本发明涉及一种具有开关控制逻辑（151）的差分总线的接收器，其具有两个具有电阻元件（7,61。，70,8和5,11，...，20,6）的分支以及开关（ 3，80），用于切换电阻元件，其中开关控制逻辑将开关置于用于通过向总线施加共模电压来确定总线上的信号的绝对电平的第一例程中，通过比较具有参考电压的第一电阻分支，通过选择正确的开关设置，以及将这些设置写入内部存储装置，以及在第二程序中，通过向总线施加共模电压来最小化两个电阻分支之间的失配通过比较第二电阻分支的电压与已修整的第一电阻分支的电压，通过选择第二分支的正确开关设置，并将这些设置写入内部存储装置。因此，接收机提供良好的平衡和共模抑制。

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