会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES
    • QUASI-DIGITAL接收器用于高速伺服系统
    • US20140146922A1
    • 2014-05-29
    • US13720623
    • 2012-12-19
    • BROADCOM CORPORATION
    • Ali NazemiMahmoud Reza AhmadiTamer AliBo ZhangMohammed Abdul-LatifNamik KocamanAfshin Momtaz
    • H04L25/02
    • H04L7/00H04L7/002H04L25/0272H04L25/0292H04L25/0296H04L25/06
    • Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.
    • 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如,用于高速解串器的接收器可以包括数字限幅器,数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。
    • 4. 发明申请
    • ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION
    • 具有可调峰值功能的模拟信号电流积分器
    • US20130215954A1
    • 2013-08-22
    • US13399675
    • 2012-02-17
    • Troy J. BeukemaJohn F. Bulzacchelli
    • Troy J. BeukemaJohn F. Bulzacchelli
    • H04L27/01H03F3/45
    • G06G7/184H03F3/45098H03F2203/45296H03F2203/45298H03F2203/45374H03F2203/45466H03F2203/45616H03F2203/45618H04L25/0296H04L25/03885
    • Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
    • 模拟信号电流积分器具有可调峰值功能。 具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿,适用于包含高级均衡功能的高数据速率接收机集成电路中的应用,如决策反馈均衡器。 例如,电流积分器电路包括电流积分放大器电路,该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应,以及峰值控制电路,用于产生控制信号,以将可调节电路元件的值调整为 当前积分器电路的工作状态的功能。 操作条件可以是指定的数据速率或通信信道特性,也可以是两者。 可调电路元件可以是退化电容器或偏置电流源。
    • 7. 发明授权
    • Method and system for a second order input intercept point (IIP2) correction
    • 二阶输入截点(IIP2)校正方法和系统
    • US07869777B2
    • 2011-01-11
    • US12200660
    • 2008-08-28
    • Hooman Darabi
    • Hooman Darabi
    • G06F3/033
    • H04L25/061H03D3/008H04B1/30H04L25/0272H04L25/0294H04L25/0296
    • In RF transceivers, a method and system for a second order input intercept point (IIP2) correction are provided. A DC offset sensor may detect DC offset voltages produced by blocker signals in “I” and “Q” signal component paths in an RF receiver. The DC offset sensor may generate control signals which may be utilized by a first and second injection circuits to generate DC offset currents that compensate for the DC offset voltages in the signal component paths. An injection circuit may utilize current drivers to generate binary weighted currents which may be added together to produce a DC offset current. The polarity of the DC offset current and the selection of which current drivers to use may be determined by the control signals. A calibration voltage may also be utilized to correct or adjust the gain in the injection circuit.
    • 在RF收发器中,提供了用于二阶输入截点(IIP2)校正的方法和系统。 DC偏移传感器可以检测RF接收机中的“I”和“Q”信号分量路径中的阻塞信号产生的DC偏移电压。 DC偏移传感器可以产生可由第一和第二注入电路利用的控制信号,以产生补偿信号分量路径中的DC偏移电压的DC偏移电流。 注入电路可以利用电流驱动器来产生可加在一起以产生DC偏移电流的二进制加权电流。 DC偏移电流的极性和使用哪些电流驱动器的选择可以由控制信号确定。 也可以使用校准电压来校正或调整注入电路中的增益。
    • 9. 发明授权
    • Data transfer control device, electronic instrument, and data transfer control method
    • 数据传输控制装置,电子仪器和数据传输控制方法
    • US07706309B2
    • 2010-04-27
    • US11073857
    • 2005-03-08
    • Yukinari ShibataTomonaga Hasegawa
    • Yukinari ShibataTomonaga Hasegawa
    • H04B1/44H04B1/56
    • H04L25/4908H04L5/1438H04L5/16H04L5/18H04L25/0274H04L25/0284H04L25/0296
    • A data transfer control device includes: a transmitter circuit; a receiver circuit; a transfer direction switch circuit which performs switching a transfer direction; a transfer direction switch indication circuit which indicates the transfer direction switch circuit to switch the transfer direction; and a code generation circuit which generates a transfer direction switch request code when a transfer direction switch request has been received from an upper layer circuit. When the transfer direction switch request has been received from the upper layer circuit, the transmitter circuit transmits the transfer direction switch request code through a serial signal line, and the transfer direction switch indication circuit indicates the transfer direction switch circuit to switch from a transmission direction to a reception direction after the transfer direction switch request code has been transmitted.
    • 数据传输控制装置包括:发射机电路; 接收机电路; 执行切换传送方向的传送方向切换电路; 传送方向切换指示电路,其指示传送方向切换电路切换传送方向; 以及代码生成电路,当从上层电路接收到传送方向切换请求时,生成传送方向切换请求代码。 当从上层电路接收到传送方向切换请求时,发送电路通过串行信号线发送传送方向切换请求码,传送方向切换指示电路表示传送方向切换电路从传送方向切换 在传送方向切换请求代码已经被发送之后到接收方向。
    • 10. 发明授权
    • Receiver for a differential data bus
    • 接收器用于差分数据总线
    • US07532046B2
    • 2009-05-12
    • US11632031
    • 2005-06-30
    • Jelle Nico WolthekCornelis Klaas WaardenburgCecilius Gerardus KwakernaatStefan Gerhard Erich Butselaar
    • Jelle Nico WolthekCornelis Klaas WaardenburgCecilius Gerardus KwakernaatStefan Gerhard Erich Butselaar
    • H03B1/00
    • H04L25/0296H03F3/45991H03F2203/45538H03F2203/45588H03F2203/45616H04L25/0274
    • The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.
    • 本发明涉及一种具有开关控制逻辑(151)的差分总线的接收器,其具有两个具有电阻元件(7,61。,70,8和5,11,...,20,6)的分支以及开关( 3,80),用于切换电阻元件,其中开关控制逻辑将开关置于用于通过向总线施加共模电压来确定总线上的信号的绝对电平的第一例程中,通过比较 具有参考电压的第一电阻分支,通过选择正确的开关设置,以及将这些设置写入内部存储装置,以及在第二程序中,通过向总线施加共模电压来最小化两个电阻分支之间的失配 通过比较第二电阻分支的电压与已修整的第一电阻分支的电压,通过选择第二分支的正确开关设置,并将这些设置写入内部存储装置。 因此,接收机提供良好的平衡和共模抑制。