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1. 发明申请

US20180076708A1 DISTRIBUTED VOLTAGE REGULATION SYSTEM FOR MITIGATING THE EFFECTS OF IR-DROP 审中-公开
公开(公告)号：US20180076708A1
公开(公告)日：2018-03-15
申请号：US15263466
申请日：2016-09-13
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Michael A. Sperling , Zeynep Toprak Deniz
IPC分类号： H02M3/07
CPC分类号： H02M3/07 , G05F1/56 , H01L23/50
摘要： A distributed voltage regulator includes multiple micro-regulators disposed in a corresponding set of circuit sectors of an integrated circuit. Each micro-regulator provides current to the corresponding circuit sector at a current injection point. The regulator also includes a control module configured to receive feedback signals corresponding to a one or more sense points within each circuit sector and provide a control signal to each micro-regulator. The control module limits load-sharing imbalance within the plurality of micro-regulators. A voltage regulator with multiple sense points includes a micro-regulator that provides current at a current injection point, and a control module that receives feedback signals corresponding to a plurality of sense points and provides a control signal to the micro-regulator. The micro-regulator may comprise a charge pump that provides a local reference voltage that enables the micro-regulator to suppress local voltage drooping during feedback transitions (e.g., while switching between different feedback signals).

2. 发明授权

US09444437B2 Circuits and methods for DFE with reduced area and power consumption 有权
标题翻译： DFE的电路和方法，减少面积和功耗
公开(公告)号：US09444437B2
公开(公告)日：2016-09-13
申请号：US14670540
申请日：2015-03-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John F. Bulzacchelli , Byungsub Kim
IPC分类号： H03K3/356 , H04L25/03 , H03K3/012
CPC分类号： H03K3/35613 , H03K3/012 , H03K3/356139 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L2025/0349
摘要： A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.
摘要翻译： 1 / n速率判决反馈均衡器（DFE）和方法包括多个分支。每个分支包括单独的加法电路，其被配置为向接收到的输入添加相应的反馈信号，以及锁存器，被配置为接收加法电路的输出，以基于时钟信号提供不同的部分位序列。反馈电路包括多路复用器，其被配置为对每个分支的不同部分比特序列进行复用以组合全速率比特序列，以及被配置为从接收到的输入提供符号间干扰（ISI）的消除。

3. 发明申请

US20150200792A1 CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION 有权
标题翻译：具有减少面积和功耗的DFE的电路和方法
公开(公告)号：US20150200792A1
公开(公告)日：2015-07-16
申请号：US14670540
申请日：2015-03-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John F. Bulzacchelli , Byungsub Kim
IPC分类号： H04L25/03
CPC分类号： H03K3/35613 , H03K3/012 , H03K3/356139 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L2025/0349
摘要： A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.
摘要翻译： 1 / n速率判决反馈均衡器（DFE）和方法包括多个分支。每个分支包括单独的加法电路，其被配置为向接收到的输入添加相应的反馈信号，以及锁存器，被配置为接收加法电路的输出，以基于时钟信号提供不同的部分位序列。反馈电路包括多路复用器，其被配置为对每个分支的不同部分比特序列进行复用以组合全速率比特序列，以及被配置为从接收到的输入提供符号间干扰（ISI）的消除。

4. 发明申请

US20150146768A1 POWER AWARE EQUALIZATION IN A SERIAL COMMUNICATIONS LINK 有权
标题翻译：串行通信链路中的功率均衡化
公开(公告)号：US20150146768A1
公开(公告)日：2015-05-28
申请号：US14088484
申请日：2013-11-25
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Hayden C. Cranford, JR. , Daniel M. Dreps , David W. Siljenberg
IPC分类号： H04L25/03
CPC分类号： H04L25/03885 , H04L25/03006 , H04L25/03114 , H04L25/03159 , H04L2025/03566 , H04L2025/03592
摘要： Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.
摘要翻译：包括发射机和接收机的串行通信链路中的功率感知均衡包括：由功率感知均衡模块确定由接收机接收的信号所需的信号眼睛宽度和所需信号眼睛高度; 识别通过串行通信链路传输的信号的一个或多个信号均衡器; 识别均衡通过串行通信链路发送的信号的一个或多个累积均衡器设置，以符合由接收机接收的信号的所需信号眼宽度和所需信号眼睛高度; 确定与所述一个或多个累积均衡器设置中的每一个相关联的功耗值; 以及根据与所述一个或多个累积均衡器设置中的每一个相关联的功耗值，将所述一个或多个信号均衡器设置为配置设置。

5. 发明申请

US20150061744A1 PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS 有权
标题翻译：用于电压调节器的优化精度校准技术
公开(公告)号：US20150061744A1
公开(公告)日：2015-03-05
申请号：US14458428
申请日：2014-08-13
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
IPC分类号： G05F1/625
CPC分类号： G05F1/59 , G05F1/625
摘要： Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
摘要翻译：提供系统和方法来调节负载电路的电源电压。例如，系统包括包括通路装置的电压调节器电路。该系统包括通道强度校准控制模块，其被配置为（i）获得指定电压调节器电路的操作条件的信息，（ii）使用获得的信息访问一个或多个查找表的访问条目，（iii）使用在所访问的条目内的信息以确定由所获得的信息指定的操作条件下负载电路可能要求的最大负载电流，并且预测足以提供所确定的最大负载电流的通道装置宽度，以及（iv ）根据预测的通道装置宽度设置通道装置的有效宽度。

6. 发明授权

US08941415B2 Edge selection techniques for correcting clock duty cycle 有权
标题翻译：用于校正时钟占空比的边沿选择技术
公开(公告)号：US08941415B2
公开(公告)日：2015-01-27
申请号：US14151998
申请日：2014-01-10
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Ankur Agrawal
IPC分类号： H03K17/00 , H03K5/156 , H03K3/017
CPC分类号： H03K17/005 , H03K3/017 , H03K5/1565
摘要： Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.
摘要翻译：提供电路和方法用于产生时钟信号和校正时钟信号中的占空比失真。用于产生时钟信号的电路包括多路复用器电路和边沿触发触发器电路。多路复用器电路选择性地输出多个输入时钟信号中的一个。边沿触发触发器检测从多路复用器电路有选择地输出的输入时钟信号的转变边缘，并且响应于该检测，对接收数据信号进行逻辑电平采样，并产生输出时钟信号在边沿触发的触发器的输出端口。多路复用器电路基于边沿触发的触发器的输出端口处的输出时钟信号的逻辑电平，选择性地将多个输入时钟信号中的一个输出到边沿触发的触发器的时钟信号端口，其被输入到多路复用器电路的选择控制端口。

7. 发明授权

US08755220B2 Hybrid superconducting-magnetic memory cell and array 失效
标题翻译：混合超导磁存储单元和阵列
公开(公告)号：US08755220B2
公开(公告)日：2014-06-17
申请号：US13943356
申请日：2013-07-16
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , William J. Gallagher , Mark B. Ketchen
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C8/14 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/44 , H01L27/18 , H01L27/222
摘要： In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
摘要翻译：在一个实施例中，本发明是混合超导磁存储器单元和阵列。存储单元的一个实施例包括磁阻元件和与磁阻元件平行布线的至少一个超导元件。在另一实施例中，所公开的配置的存储器单元被布置成形成存储器阵列。

8. 发明申请

US20130208782A1 TIME DOMAIN ANALOG MULTIPLICATION TECHNIQUES FOR ADJUSTING TAP WEIGHTS OF FEED-FORWARD EQUALIZERS 有权
标题翻译：用于调整进给均衡器的TAP权重的时域模拟多路复用技术
公开(公告)号：US20130208782A1
公开(公告)日：2013-08-15
申请号：US13763659
申请日：2013-02-09
申请人： International Business Machines Corporation
发明人： Ankur Agrawal , John F. Bulzacchelli
IPC分类号： H04L27/01
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to a given FFE tap during the integration period to enable the given FFE tap during a portion of the integration period in which the gating control signal overlaps the integration period so as to effectively multiply the data signal input to the given FFE tap with an FFE coefficient value corresponding to a period of overlap between the gating control signal and the integration period.
摘要翻译：提供前馈均衡器（FFE）电路和方法，其实现时域模拟乘法以调整FFE抽头权重。例如，一种方法包括将数据信号输入到电流积分加法电路的FFE抽头，其中数据信号是模拟输入数据信号的时间延迟版本。在电流积分夏季电路的复位期间，将电容充电至预充电电平。在积分积分电路的积分期间，由每个FFE抽头产生输出电流。来自FFE抽头的输出电流在积分期间共同对电容进行充电或放电。在积分周期期间，门控控制信号被施加到给定的FFE抽头，以便在选通控制信号与积分周期重叠的积分周期的一部分期间实现给定的FFE抽头，以便有效地将输入的数据信号乘以给定的 FFE抽头具有对应于门控控制信号和积分周期之间的重叠周期的FFE系数值。

9. 发明授权

US10924310B2 Transmitter with fully re-assignable segments for reconfigurable FFE taps 有权
公开(公告)号：US10924310B2
公开(公告)日：2021-02-16
申请号：US16277392
申请日：2019-02-15
申请人： International Business Machines Corporation
发明人： Zeynep Toprak-Deniz , John F. Bulzacchelli , Herschel A. Ainspan , Jonathan E. Proesel , Mounir Meghelli
IPC分类号： H04L27/01
摘要： Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

10. 发明授权

US10693429B2 Dynamic phased array tapering without phase recalibration 有权
公开(公告)号：US10693429B2
公开(公告)日：2020-06-23
申请号：US16354850
申请日：2019-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John F. Bulzacchelli , Bodhisatwa Sadhu , Alberto Valdes Garcia
IPC分类号： H01Q3/36 , H03G3/30 , H01Q21/22 , H01Q3/28 , H03F3/19 , H03F3/45 , H04B1/48 , H01Q1/52 , H03F3/195 , H04B7/06
摘要： Methods and systems for phased array tapering include setting a gain at a phase-invariant variable gain amplifier in each of a set of front-ends of a phased array transceiver, to perform tapering of beam pattern side lobes. Setting the gain includes setting a first gain at a first stage of the phase-invariant variable gain amplifier and setting a second gain at a second stage of the phase-invariant variable gain amplifier. A dependency of a phase shift of the first stage on the gain of the first stage is equal to and opposite a dependency of a phase shift of the second stage on the gain of the second stage.

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