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61. 发明授权

US08684802B1 Method and apparatus for balancing thermal variations across a set of computer systems 有权
标题翻译：用于平衡一组计算机系统的热变化的方法和装置
公开(公告)号：US08684802B1
公开(公告)日：2014-04-01
申请号：US11588788
申请日：2006-10-27
申请人： Kenny C. Gross , Keith A. Whisnant , Ramakrishna C. Dhanekula , Steven F. Zwinger
发明人： Kenny C. Gross , Keith A. Whisnant , Ramakrishna C. Dhanekula , Steven F. Zwinger
IPC分类号： H05K7/20 , G05B13/00
CPC分类号： H05K7/20836 , G06F1/206
摘要： A system that balances thermal variations within a set of computer systems in a datacenter. During operation, the system obtains a thermal flux map for the set of computer systems. The system then analyzes the thermal flux map to determine whether imbalances exist in the thermal flux across the set of computer systems. If so, the system can adjust: (1) the scheduling of loads across the set of computer systems, and/or (2) air conditioning within the datacenter, so that the thermal flux is more balanced across the set of computer systems.
摘要翻译：一种平衡数据中心内的一组计算机系统内的热变化的系统。在操作期间，系统获得该组计算机系统的热通量图。然后，该系统分析热通量图，以确定跨越该组计算机系统的热通量中是否存在不平衡。如果是这样，系统可以调整：（1）跨计算机系统集中的负载调度，和/或（2）数据中心内的空调，以使整个计算机系统的热通量更加平衡。

62. 发明授权

US08645632B2 Speculative writestream transaction 有权
标题翻译：投机书写交易
公开(公告)号：US08645632B2
公开(公告)日：2014-02-04
申请号：US12365732
申请日：2009-02-04
申请人： Robert E. Cypher , Haakan E. Zeffer , Anders Landin
发明人： Robert E. Cypher , Haakan E. Zeffer , Anders Landin
IPC分类号： G06F12/06
CPC分类号： G06F12/0817
摘要： Embodiments of the present invention provide a system that performs a speculative writestream transaction. The system starts by receiving, at a home node, a writestream ordered (WSO) request to start a WSO transaction from a processing subsystem. The WSO request identifies a cache line to be written during the WSO transaction. The system then sends an acknowledge signal to the processing subsystem to enable the processing subsystem to proceed with the WSO transaction. During the WSO transaction, the system receives a second WSO request to start a WSO transaction. The second WSO request identifies the same cache line as to be written during the subsequent WSO transaction. In response to receiving the second WSO request, the system sends an abort signal to cause the processing subsystem to abort the WSO transaction.
摘要翻译：本发明的实施例提供一种执行推测性写入事务的系统。系统通过在家庭节点处接收从处理子系统开始WSO事务的写入序列（WSO）请求来开始。 WSO请求标识要在WSO事务期间写入的高速缓存行。然后系统向处理子系统发送确认信号，使处理子系统能够进行WSO交易。在WSO事务期间，系统收到第二个WSO请求以启动WSO事务。第二个WSO请求标识在随后的WSO事务期间写入相同的高速缓存行。响应于接收到第二个WSO请求，系统发送中止信号使处理子系统中止WSO事务。

63. 发明授权

US08644759B2 Offset cancellation for DC isolated nodes 有权
标题翻译： DC隔离节点的偏移消除
公开(公告)号：US08644759B2
公开(公告)日：2014-02-04
申请号：US12349011
申请日：2009-01-06
申请人： Justin M. Schauer , Robert David Hopkins , Robert J. Drost
发明人： Justin M. Schauer , Robert David Hopkins , Robert J. Drost
IPC分类号： H04B5/00
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/45475 , H03F3/45973 , H03F2200/534 , H03F2200/537 , H03F2200/54 , H03F2200/541 , H03F2203/45101 , H03F2203/45212 , H03F2203/45518 , H03F2203/45524 , H03F2203/45528 , H04B5/0031
摘要： Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.
摘要翻译：在与输入到放大器的数据信号直流隔离的高性能放大器的输入上开发的浮动电压上的偏移电压通过在输入节点和预定电位之间连接高电阻元件而被消除，在邻近通信系统中特别有用，其中两个芯片通过在两个芯片中共同形成的电容或电感耦合电路连接。电阻元件可以是连接在节点和期望偏置电压之间的截止MOS晶体管，或者其栅极和漏极连接到电位的MOS晶体管。可以将多个偏置电压分配给所有接收器，并由多路复用器本地选择以应用于接收器的一个或两个输入节点。当电阻元件与数据速率相比具有长时间常数或电阻元件是非线性时，接收器输出也可以用作预定电位。

64. 发明授权

US08640123B2 Apparatus and method for simulating software installation using software dependency map 有权
标题翻译：使用软件依赖关系图模拟软件安装的装置和方法
公开(公告)号：US08640123B2
公开(公告)日：2014-01-28
申请号：US13157091
申请日：2011-06-09
申请人： Michael J. Wookey
发明人： Michael J. Wookey
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G06F8/658
摘要： A virtual installation map, and method involving installing a software functionality using the same, the virtual installation map including a first software installation map including a plurality of software elements representative of a related software file, the software elements also including at least one dependency to another software element. The virtual installation map further including a second software installation map also including a second plurality of software elements representative of related software file along with related dependencies. The first and second software installation maps may be hosted in separate databases and may relate to software products provided by different vendors. One or both software installation maps may include a pointer or other reference to the other installation map thereby providing a virtual installation map, in one example.
摘要翻译：虚拟安装图和涉及使用其安装软件功能的方法，所述虚拟安装映射包括包括表示相关软件文件的多个软件元素的第一软件安装映射，所述软件元素还包括至少一个依赖于另一个软件元素。虚拟安装映射还包括第二软件安装映射，还包括表示相关软件文件的第二多个软件元素以及相关的依赖性。第一和第二软件安装地图可以托管在单独的数据库中，并且可以涉及由不同供应商提供的软件产品。在一个示例中，一个或两个软件安装映射可以包括指向其他安装映射的指针或其他引用，从而提供虚拟安装映射。

65. 发明授权

US08635048B2 Methods for characterizing vibration of a rack structure 有权
标题翻译：表征机架结构振动的方法
公开(公告)号：US08635048B2
公开(公告)日：2014-01-21
申请号：US13475527
申请日：2012-05-18
申请人： Kenny C. Gross , Aleksey M. Urmanov , Anton A. Bougaev , David K. McElfresh
发明人： Kenny C. Gross , Aleksey M. Urmanov , Anton A. Bougaev , David K. McElfresh
IPC分类号： G01H13/00
CPC分类号： G01N29/12 , G01H1/14 , G01H13/00
摘要： A system for characterizing vibration of a rack structure having at least one hard disk drive disposed therein and a vibration exciter operatively associated with the rack structure includes one or more computers. The one or more computers are configured to command the vibration exciter to provide vibration input to the rack structure and to command a plurality of reads from the at least one hard disk drive such that, for each of the plurality of reads, data stored on the at least one hard disk drive is retrieved from the at least one hard disk drive. The one or more computers are also configured to obtain read rate information related to the plurality of reads and to identify at least one resonant frequency of the rack structure based on the read rate information.
摘要翻译：用于表征具有设置在其中的至少一个硬盘驱动器的机架结构的振动的系统和与所述机架结构可操作地相关联的振动激励器包括一个或多个计算机。一个或多个计算机被配置为命令振动激励器向机架结构提供振动输入并且从至少一个硬盘驱动器命令多个读取，使得对于多个读取中的每一个，存储在从至少一个硬盘驱动器检索至少一个硬盘驱动器。一个或多个计算机还被配置为获得与多个读取相关的读取速率信息，并且基于读取速率信息来识别机架结构的至少一个谐振频率。

66. 发明授权

US08627302B2 Sampling based runtime optimizer for efficient debugging of applications 有权
标题翻译：基于采样的运行时优化器，用于应用程序的高效调试
公开(公告)号：US08627302B2
公开(公告)日：2014-01-07
申请号：US11945989
申请日：2007-11-27
申请人： William Y. Chen , Jiwei Lu
发明人： William Y. Chen , Jiwei Lu
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3628 , G06F11/3461 , G06F11/3476 , G06F11/3632 , G06F11/3664 , G06F2201/86 , G06F2201/865
摘要： A method of reproducing runtime environment for debugging an application includes reading an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of events, actions, and a time mark of occurrence for each of the actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file. Further, the method includes running the application, attaching an optimizer, and triggering each of the actions to occur at a time mark of occurrence associated with each of the actions. Then, each of the actions and associated events is analyzed by comparing the events produced by running the application with the events in the optimizer file. If a fault is produced by the triggering, a debugger is invoked to analyze the fault.
摘要翻译：再现用于调试应用的运行时环境的方法包括从非易失性存储介质读取优化器文件。优化程序文件包括运行时环境，应用程序定义信息和日志。日志包括每个操作的事件，操作和发生时间标记的摘要。然后定义用于调试应用程序的运行时环境，并使用优化程序文件中的应用程序定义信息设置应用程序运行时间。此外，该方法包括运行应用程序，附加优化器以及触发在与每个动作相关联的发生的时间标记处发生的每个动作。然后，通过将运行应用程序生成的事件与优化程序文件中的事件进行比较来分析每个操作和关联事件。如果触发产生故障，则调用调试器来分析故障。

67. 发明授权

US08627040B2 Processor-bus-connected flash storage paging device using a virtual memory mapping table and page faults 有权
标题翻译：处理器总线连接的闪存存储寻呼设备使用虚拟内存映射表和页面故障
公开(公告)号：US08627040B2
公开(公告)日：2014-01-07
申请号：US13731760
申请日：2012-12-31
申请人： Oracle International Corporation
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F12/10 , G06F13/28 , G06F2212/2022 , G06F2212/214
摘要： A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address.
摘要翻译：一种使用处理器总线连接的闪速存储模块（PFSM）作为第一寻呼装置和硬盘驱动器（HDD）作为第二寻呼装置访问处理器的虚拟存储器的方法，所述方法包括：分配第一地址分区和用于处理器的软件应用的虚拟存储器的第二地址分区分别对第一寻呼设备和第二寻呼设备进行识别，以响应于虚拟存储器触发的页面错误来识别第一寻呼设备中的虚拟存储器页面通过软件应用程序，响应于页面错误向PFSM发送访问虚拟存储器页面的页面访问请求，以及基于由PFSM发出的处理器总线的命令并结合执行的操作从PFSM接收虚拟存储器页面使用闪存页地址在闪存中闪存存取。

68. 发明授权

US08612978B2 Code execution utilizing single or multiple threads 有权
标题翻译：使用单线程或多线程的代码执行
公开(公告)号：US08612978B2
公开(公告)日：2013-12-17
申请号：US12634855
申请日：2009-12-10
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.
摘要翻译：使用主要硬件线程执行程序。在执行期间，指令指定执行使用工作人员硬件线程的部分。如果处理器状态指示器设置为多线程，则使用工作程序硬件线程执行指定的部分。然而，如果处理器状态指示器设置为单线程，则使用主硬件线程作为子例程来执行指定部分。主要硬件线程可以通过将主要硬件线程的参数数据寄存器或存储器位置复制到工作人员硬件线程的等效参数数据寄存器或存储器位置来将参数数据传递给工作者硬件线程。类似地，工作者硬件线程可以通过将工作者硬件线程的返回值寄存器或存储器位置复制到主硬件线程的等效返回值寄存器或存储器位置来将返回值传递给主要硬件线程。

69. 发明授权

US08606997B2 Cache hierarchy with bounds on levels accessed 有权
标题翻译：缓存层次结构，并且访问级别的边界
公开(公告)号：US08606997B2
公开(公告)日：2013-12-10
申请号：US12343065
申请日：2008-12-23
申请人： Robert Cypher , Haakan Zeffer , Anders Landin
发明人： Robert Cypher , Haakan Zeffer , Anders Landin
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0862
摘要： The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
摘要翻译：本发明涉及一种管理多级高速缓冲存储器系统中的数据的系统。某些高速缓存数据被指定并仅存储在多级缓存的特定级别中，从而绕过多级高速缓存的其他级别。在多处理器环境中，本发明包括高速缓存一致性操作或与仅存储在多级缓存的特定级别中的数据相关的消息。

70. 发明授权

US08601101B1 Cluster communications framework using peer-to-peer connections 有权
标题翻译：使用对等连接的群集通信框架
公开(公告)号：US08601101B1
公开(公告)日：2013-12-03
申请号：US10878785
申请日：2004-06-28
申请人： Servesh Pratap Singh
发明人： Servesh Pratap Singh
IPC分类号： G06F15/173
CPC分类号： H04L69/40 , H04L67/10 , H04L67/1031
摘要： Various embodiments of a system and method for each node in a cluster including a peer-to-peer communication channel compiling and maintaining its own cluster membership are disclosed. In one embodiment, each cluster node may be coupled to every other node and commonly-accessible storage through a network. When a node starts up and attempts to join the cluster, it may access cluster information data stored in the commonly-accessible storage. This information may include a list of all nodes that are potential cluster members. Based on the cluster membership information, the joining node may request a peer-to-peer connection with each potential cluster member. When such a request results in establishment of a connection, the joining node may add the name of the target node to its cluster membership list. Likewise, when a member node grants a connection to a node, it may add the joining node to its cluster membership list.
摘要翻译：公开了包括对等通信信道的群集中的每个节点的系统和方法的各种实施例，其编译和维护其自己的群集成员。在一个实施例中，每个群集节点可以通过网络耦合到每个其他节点和通常可访问的存储。当节点启动并尝试加入群集时，它可以访问存储在普通可访问存储中的群集信息数据。该信息可以包括作为潜在集群成员的所有节点的列表。基于集群成员关系信息，加入节点可以请求与每个潜在集群成员的对等连接。当这样的请求导致建立连接时，加入节点可以将目标节点的名称添加到其集群成员列表。同样，当成员节点授予与节点的连接时，它可以将加入节点添加到其集群成员列表。

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