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61. 发明授权

US5506431A Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications 失效
标题翻译：双沟槽通道加速隧道电子（DPT-CATE）单元，用于存储器应用
公开(公告)号：US5506431A
公开(公告)日：1996-04-09
申请号：US243507
申请日：1994-05-16
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L29/423 , H01L29/788 , H01L29/78 , G11C13/00
CPC分类号： H01L29/7885 , H01L29/4232
摘要： A structure for low voltage, high density, non-volatile memory cell, with ability to write electrically using the CACT or Channel Accelerated Carrier Tunneling method for programming memories and erase electrically by tunneling, having separate regions for write and erase for high reliability, is described. These cells have the ability to write by transferring charge to the storage gate using the majority carriers in the channel of the MOS transistor, eliminating the need for generation of high fields needed for the hot electron EPROM write method used in the prior art flash memories. In addition the use of the carrier velocity to enhance the write process reduce the need for the high write -voltages on the gates as compared to the present EEPROM and EPROM write memories.
摘要翻译：一种用于低电压，高密度，非易失性存储单元的结构，具有使用CACT或通道加速载波隧道方式进行电气写入的能力，用于通过隧道编程存储器和电擦除，具有用于写入和擦除的独立区域以实现高可靠性，描述。这些单元具有通过使用MOS晶体管的通道中的多数载流子将电荷转移到存储栅来写入的能力，从而无需生成现有技术闪存中使用的热电子EPROM写入方法所需的高场。此外，与当前的EEPROM和EPROM写入存储器相比，使用载波速度来增强写入过程减少了对门上的高写入电压的需要。

62. 发明授权

US5252507A Very high density wafer scale device architecture 失效
标题翻译：非常高密度的晶圆秤设备架构
公开(公告)号：US5252507A
公开(公告)日：1993-10-12
申请号：US502898
申请日：1990-03-30
申请人： James W. Hively , Mammen Thomas , Richard L. Bechtel
发明人： James W. Hively , Mammen Thomas , Richard L. Bechtel
IPC分类号： G01R31/317 , G11C5/02 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/66 , H01L21/82 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/0207 , G11C29/006 , G11C5/025
摘要： This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.
摘要翻译：本发明涉及晶片尺寸集成电路的设计和制造。晶片尺寸集成电路的较低层包括电隔离的重复块，例如电路元件的逻辑元件或块。上导电层包括数据和地址总线结构。位于上层和下层之间的自由通过层可以被图案化以实现多种目的。通孔层的图案化避免了将总线结构连接到有缺陷的元件或块，建立元件的地址，并建立寻址结构和数据结构的组织（对于存储晶圆，字长，单词数量和数量每个银行的单词）。通孔图案被图案化以在测试之后将上部总线连接到较低金属级别中的选定区域（测试使用常规技术）以获得良好和坏的元件。

63. 发明授权

US4800171A Method for making bipolar and CMOS integrated circuit structures 失效
标题翻译：制造双极和CMOS集成电路结构的方法
公开(公告)号：US4800171A
公开(公告)日：1989-01-24
申请号：US104459
申请日：1987-10-02
申请人： Ali Iranmanesh , Mammen Thomas
发明人： Ali Iranmanesh , Mammen Thomas
IPC分类号： H01L21/033 , H01L21/8249 , H01L21/365
CPC分类号： H01L21/033 , H01L21/8249 , Y10S148/01 , Y10S148/011 , Y10S148/117 , Y10S148/124
摘要： An improved method is described for constructing one or more integrated circuit components including bipolar and MOS devices on a silicon substrate without damaging areas of the substrate wherein active elements of the integrated circuit components will be formed. The method comprises forming multilayer pedestals of masking materials over the active regions of the substrate and subsequently removing these masking materials using wet etching to avoid damage to the substrate by dry etching.
摘要翻译：描述了一种改进的方法，用于在硅衬底上构造包括双极和MOS器件的一个或多个集成电路部件，而不损坏将形成集成电路部件的有源元件的衬底区域。该方法包括在衬底的有源区上形成掩模材料的多层基座，随后使用湿蚀刻去除这些掩模材料，以避免通过干蚀刻对衬底的损伤。

64. 发明授权

US4707456A Method of making a planar structure containing MOS and bipolar transistors 失效
标题翻译：制造包含MOS和双极晶体管的平面结构的方法
公开(公告)号：US4707456A
公开(公告)日：1987-11-17
申请号：US777153
申请日：1985-09-18
申请人： Mammen Thomas , Matthew Weinberg
发明人： Mammen Thomas , Matthew Weinberg
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L21/8249 , H01L27/06 , H01L21/225
CPC分类号： H01L21/763 , H01L21/76202 , H01L21/8249 , H01L27/0623
摘要： A highly planarized integrated circuit structure having at least one bipolar device and at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with portions defined therein respectively for formation of a collector region and a base/emitter region for a bipolar device and a source/gate/drain region for an MOS device. All of the contacts of the devices are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.
摘要翻译：描述了具有至少一个双极器件和至少一个MOS器件的高度平坦化的集成电路结构以及制造该结构的方法。该结构包括其上分别形成有部分限定在其中的部分的集成区域和用于双极器件的基极/发射极区域以及用于MOS器件的源极/栅极/漏极区域的部分，其上生长有场氧化物的衬底。器件的所有触点都是使用填充场氧化物中限定部分的多晶硅形成的，从而形成高度平坦化的结构。

65. 发明授权

US4696095A Process for isolation using self-aligned diffusion process 失效
标题翻译：使用自对准扩散过程进行隔离的过程
公开(公告)号：US4696095A
公开(公告)日：1987-09-29
申请号：US844908
申请日：1986-03-27
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L21/76 , H01L21/308 , H01L21/31 , H01L21/74 , H01L21/762
CPC分类号： H01L21/74 , H01L21/308 , H01L21/76208 , H01L21/76216
摘要： A process is disclosed for improving the isolation between semi-oxide insulated devices, formed on mesa structures. In the fabrication of such devices, a silicon substrate is provided. Patterned regions of one type of conductivity are formed in a major surface of the substrate and an epitaxial layer of silicon is formed on the substrate over the major surface. A patterned mask layer is formed on the epitaxial layer and is etched to expose portions of the epitaxial layer. The exposed portions of the epitaxial layer are removed to form the mesa structures, which overlie the doped patterned regions. Regions of opposite conductivity, called channel stops, are then formed in the substrate between the patterned regions. After filling in the areas between the mesa structures with a field oxide, the devices (bipolar or MOS transistors) are formed on the mesa structures.The process of the invention utilizes as a mask structure a mask having a combination of properties (composition and thickness) related to the subequent processing. The mask permits use of an anisotropic etchant to define the mesa structures and to undercut the mask. An oxide layer is formed on the side walls of the mesa structures and on those portions of the substrate exposed during the mesa-defining step. Those portions of the oxide layer underlying openings in the mask structure are removed to expose portions of the substrate, which encompass regions between the doped patterned regions. The channel stop dopant is introduced into the regions between the patterned regions.
摘要翻译：公开了一种用于改善在台面结构上形成的半氧化物绝缘装置之间的隔离的方法。在这样的器件的制造中，提供硅衬底。在衬底的主表面上形成一种导电类型的图形区域，并且在主表面上的衬底上形成硅外延层。在外延层上形成图案化的掩模层，并被蚀刻以暴露外延层的部分。去除外延层的暴露部分以形成覆盖掺杂图案区域的台面结构。然后在图案化区域之间的衬底中形成具有相反电导率的区域，称为通道停止点。在用场氧化物填充台面结构之间的区域之后，在台面结构上形成器件（双极或MOS晶体管）。本发明的方法利用具有与子级处理相关的性质（组成和厚度）的组合的掩模作为掩模结构。掩模允许使用各向异性蚀刻剂来限定台面结构并且掩盖掩模。在台面结构的侧壁和在台面界定步骤期间露出的基板的那些部分上形成氧化物层。去除掩模结构中的开口下方的氧化物层的那些部分，以暴露包含掺杂图案区域之间的区域的衬底的部分。通道阻挡掺杂剂被引入到图案化区域之间的区域中。

66. 发明授权

US4669180A Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling 失效
标题翻译：使用多晶硅形成发射极耦合逻辑双极性存储单元的方法用于耦合的肖特基二极管
公开(公告)号：US4669180A
公开(公告)日：1987-06-02
申请号：US683431
申请日：1984-12-18
申请人： Mammen Thomas , Wen C. Ko
发明人： Mammen Thomas , Wen C. Ko
IPC分类号： H01L27/082 , G11C11/411 , H01L21/285 , H01L21/8222 , H01L21/8229 , H01L27/10 , H01L27/102 , H01L21/44
CPC分类号： H01L27/1025 , H01L21/28537 , H01L21/8222 , Y10S148/14 , Y10S148/147
摘要： An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to coupled the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.
摘要翻译：公开了一种改进的ECL双极存储器单元，其包括使用肖特基二极管将触发器电路中的存储晶体管的各个集电极连接到位线，以防止ECL单元的锁存; 以及电路中的晶体管的反相，以提供用于α罢工保护的埋地发射器结构。在优选实施例中，肖特基二极管和用于将单元耦合到字线之一的负载装置（例如电阻器或负载晶体管）使用多晶硅来制造，以便于电池的构造，减少所需的触点总数，以及提高细胞的速度。

67. 发明授权

US4635230A Emitter coupled logic bipolar memory cell 失效
标题翻译：发射极耦合逻辑双极性存储单元
公开(公告)号：US4635230A
公开(公告)日：1987-01-06
申请号：US683287
申请日：1984-12-18
申请人： Mammen Thomas , Wen C. Ko
发明人： Mammen Thomas , Wen C. Ko
IPC分类号： H01L27/082 , G11C11/411 , H01L21/285 , H01L21/8222 , H01L21/8229 , H01L27/10 , H01L27/102 , G11C11/40
CPC分类号： H01L21/28537 , H01L27/1025
摘要： An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.
摘要翻译：公开了一种改进的ECL双极存储器单元，其包括使用肖特基二极管将触发器电路中的存储晶体管的各个集电极连接到位线，以防止ECL单元的锁存; 以及电路中的晶体管的反相，以提供用于α罢工保护的埋地发射器结构。在优选实施例中，肖特基二极管和用于将单元耦合到字线之一的负载装置（例如电阻器或负载晶体管）使用多晶硅来制造以便于电池的构造，减少所需的触点总数，以及提高细胞的速度。

68. 发明申请

US20220303220A1 Delaying Layer 2 Frame Transmission 有权
公开(公告)号：US20220303220A1
公开(公告)日：2022-09-22
申请号：US17834097
申请日：2022-06-07
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L47/24 , H04L69/32 , H04L69/324 , H04L47/125 , H04L49/25 , G06F13/40 , G06F13/42 , H04L45/74
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

69. 发明申请

US20220218546A1 Patient Puller 有权
公开(公告)号：US20220218546A1
公开(公告)日：2022-07-14
申请号：US17710732
申请日：2022-03-31
申请人： Mammen Thomas , Sarah Peter , Elizabeth Thomas
发明人： Mammen Thomas , Sarah Peter , Elizabeth Thomas
IPC分类号： A61G7/10
摘要： A mechanism using a motor, and a rolling tube or rod of sufficient strength to apply a pull force on one side of a sheet on the bed with the patient lying on the sheet is provided to help turn patients on his side with little manual effort. Patients having mobility issues under care in homes, nursing-homes or hospitals have to be turned on their sides often to reduce formation of bed sores among other reasons. Currently this is done manually by nurses or caregivers turning the patient by pulling up on one side of the sheet to turn the patient on his side. This simple but strenuous operation has been the cause of back problems for many caregivers. The current invention is a way to reduce or eliminate this injury to caregivers by providing a mechanized help for the patient turning operation.

70. 发明申请

US20220100694A1 PCI Express to PCI Express based low latency interconnect scheme for clustering systems 有权
公开(公告)号：US20220100694A1
公开(公告)日：2022-03-31
申请号：US17525837
申请日：2021-11-12
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/42 , H04L12/931 , G06F13/40
摘要： PCI-Express (PCIE) is a Bus or I/O interconnect standard typically used for communication between a PCIE enabled computing system having a root complex and a plurality of peripheral devices, where the PCIE Bus may include a PCIE switch with a single inbound PCIE port. An outbound PCIE port on the root complex of the computing system connecting to the single inbound PCIE port of the PCIE switch. The invention describes a PCIE based interconnect scheme using a PCIE network switch to enable switching and inter-connection between multiple PCIE enabled computing systems to form a cluster for data transfer using PCIE protocol. For this, an outbound port enabled for interconnection, on each of the plurality of PCIE based computing systems in the cluster connect to one of a plurality of inbound PCIE ports on the PCIE network switch, enabling communication between the PCIE based computing systems of the cluster.

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