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61. 发明授权

US07629833B2 Power supply apparatus of semiconductor integrated circuit 失效
标题翻译：半导体集成电路供电装置
公开(公告)号：US07629833B2
公开(公告)日：2009-12-08
申请号：US11822269
申请日：2007-07-03
申请人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F1/28
摘要： A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance component in response to an input of the control signal, controls the level of the power supplied from the outside, and supplies the power having the controlled level to circuit blocks.
摘要翻译：半导体集成电路的电源装置包括功率控制装置，其检测从外部供给的电力的电平，并输出作为关于检测电平的信息的控制信号;以及电源装置，其响应于控制信号的输入控制从外部提供的电力的电平，并将具有受控电平的电力提供给电路块。

62. 发明授权

US08013593B2 Voltage measuring apparatus for semiconductor integrated circuit and voltage measuring system having the same 有权
标题翻译：具有该半导体集成电路和电压测量系统的电压测量装置
公开(公告)号：US08013593B2
公开(公告)日：2011-09-06
申请号：US11961988
申请日：2007-12-20
申请人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
IPC分类号： G01R25/00
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考时钟;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元生成的延迟时钟信号相关联的相位，区域之间的电平。

63. 发明授权

US07646223B2 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US07646223B2
公开(公告)日：2010-01-12
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

64. 发明申请

US20070194818A1 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US20070194818A1
公开(公告)日：2007-08-23
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

65. 发明申请

US20110128043A1 OUTPUT DRIVER 有权
标题翻译：输出驱动器
公开(公告)号：US20110128043A1
公开(公告)日：2011-06-02
申请号：US12832167
申请日：2010-07-08
申请人： Ic-Su OH , Hyung-Soo Kim , Chang-Kun Park
发明人： Ic-Su OH , Hyung-Soo Kim , Chang-Kun Park
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.
摘要翻译：半导体器件的输出驱动器包括驱动晶体管和体偏置提供单元。驱动晶体管并联耦合，并配置成驱动输出端。身体偏置提供单元被配置为向驱动晶体管提供至少两个级别的相应身体偏置。

66. 发明授权

US08503251B2 Semiconductor memory device having pipe latch circuit for storing output data during read operation and method for operating the same 有权
标题翻译：具有用于在读取操作期间存储输出数据的管锁存电路的半导体存储器件及其操作方法
公开(公告)号：US08503251B2
公开(公告)日：2013-08-06
申请号：US12881813
申请日：2010-09-14
申请人： Hyung-Soo Kim , Ki-Myung Kyung , Ic-Su Oh , Chang-Kun Park
发明人： Hyung-Soo Kim , Ki-Myung Kyung , Ic-Su Oh , Chang-Kun Park
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/04 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device includes a memory bank configured to output stored data in response to a column selection signal, a plurality of data latching units configured to latch the data outputted from the memory bank in response to an input control signal which is generated according to the column selection signal, and output the latched data in response to an output control signal, a time measurement unit configured to measure a time from an activation of the input control signal to an activation of the output control signal and generate a delay control signal, and an activation control unit configured to control an activation time of the column selection signal in response to the delay control signal.
摘要翻译：一种半导体存储器件，包括响应于列选择信号输出存储数据的存储器组，多个数据锁存单元，用于响应于根据该存储器块生成的输入控制信号，锁存从存储体输出的数据列选择信号，并且响应于输出控制信号输出锁存数据;时间测量单元，被配置为测量从激活输入控制信号到激活输出控制信号的时间，并产生延迟控制信号;以及激活控制单元，被配置为响应于延迟控制信号来控制列选择信号的激活时间。

67. 发明授权

US08035418B2 Output driver 有权
标题翻译：输出驱动
公开(公告)号：US08035418B2
公开(公告)日：2011-10-11
申请号：US12832167
申请日：2010-07-08
申请人： Ic-Su Oh , Hyung-Soo Kim , Chang-Kun Park
发明人： Ic-Su Oh , Hyung-Soo Kim , Chang-Kun Park
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.
摘要翻译：半导体器件的输出驱动器包括驱动晶体管和体偏置提供单元。驱动晶体管并联耦合，并配置成驱动输出端。身体偏置提供单元被配置为向驱动晶体管提供至少两个级别的相应身体偏置。

68. 发明授权

US09013460B2 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US09013460B2
公开(公告)日：2015-04-21
申请号：US12982179
申请日：2010-12-30
申请人： Hyung-Soo Kim
发明人： Hyung-Soo Kim
IPC分类号： G09G5/00 , G06F3/038 , G09G3/32
CPC分类号： G09G3/3225 , G09G3/3233 , G09G3/3283 , G09G3/3291 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/08
摘要： A display device and a method of driving the display device are disclosed. The display device includes first and second data drivers. The first data driver is configured to generate data voltages for the pixels based on first image data. The second data driver is configured to generate current voltages for the pixels based on second image data. One of the first and second data drivers may be disposed outside of a display panel.
摘要翻译：公开了一种显示装置和驱动显示装置的方法。显示装置包括第一和第二数据驱动器。第一数据驱动器被配置为基于第一图像数据生成用于像素的数据电压。第二数据驱动器被配置为基于第二图像数据生成用于像素的电流电压。第一和第二数据驱动器中的一个可以设置在显示面板的外部。

69. 发明授权

US08716714B2 Display device having electrostatic discharge protection circuit and manufacturing method thereof 有权
标题翻译：具有静电放电保护电路的显示装置及其制造方法
公开(公告)号：US08716714B2
公开(公告)日：2014-05-06
申请号：US13481714
申请日：2012-05-25
申请人： Hyung-Soo Kim , In-Ho Choi
发明人： Hyung-Soo Kim , In-Ho Choi
IPC分类号： H01L29/04 , H01L27/12 , H01L29/49 , H01L29/66 , H01L29/786 , G02F1/1362
CPC分类号： H01L27/12 , G02F1/136204 , G02F1/136227 , G02F1/13624 , G02F2202/104 , H01L27/1214 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621
摘要： A method of manufacturing a display device including an electrostatic discharge protection circuit, the method including: forming an amorphous silicon layer on a substrate; crystallizing a partial region of the amorphous silicon layer into a polycrystalline silicon layer; and forming at least one transistor on the amorphous silicon layer that was not crystallized into the polycrystalline layer, wherein the electrostatic discharge protection circuit comprises the at least one transistor.
摘要翻译：一种制造包括静电放电保护电路的显示装置的方法，所述方法包括：在基板上形成非晶硅层; 将所述非晶硅层的部分区域结晶成多晶硅层; 以及在所述非晶硅层上形成至少一个晶体管，所述至少一个晶体管未结晶到所述多晶层中，其中所述静电放电保护电路包括所述至少一个晶体管。

70. 发明授权

US08593208B2 Phase mixer and delay locked loop including the same 有权
标题翻译：相位混合器和延迟锁定环包括相同
公开(公告)号：US08593208B2
公开(公告)日：2013-11-26
申请号：US13353716
申请日：2012-01-19
申请人： Hyung-Soo Kim
发明人： Hyung-Soo Kim
IPC分类号： H03K17/00
CPC分类号： H03L7/0814 , H03K5/131 , H03K5/135 , H03K2005/00052
摘要： A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node.
摘要翻译：相位混合器包括：第一驱动器，被配置为以由第一设定值确定的驱动力将第一输入信号驱动到混合节点;第二驱动器，被配置为以由第一设定值确定的驱动力驱动第二输入信号到混合节点第二设定值和被配置为控制混合节点处的转换速率的转换速率控制单元。

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