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1. 发明授权

US08975999B2 Transformer using symmetrical printing pattern 有权
标题翻译：变压器采用对称印刷图案
公开(公告)号：US08975999B2
公开(公告)日：2015-03-10
申请号：US14342788
申请日：2011-11-07
申请人： Byung Joo Kang , Sung Hun Ahn , Ho Yong Hwang , Chang Kun Park
发明人： Byung Joo Kang , Sung Hun Ahn , Ho Yong Hwang , Chang Kun Park
IPC分类号： H01F5/00 , H01F27/28 , H05K1/16 , H05K3/22
CPC分类号： H01F27/2804 , H01F27/40 , H01F2027/2814 , H05K1/165 , H05K3/222 , H05K2203/049
摘要： Disclosed is a transformer using a symmetrical printing pattern which includes: a substrate; a plurality of first printing lines printed at predetermined distances on the substrate; a plurality of second printing lines printed at predetermined distances on the substrate; first bonding wires connecting the first printing lines; and second bonding wires connecting the second printing lines, in which the first printing lines and the second printing lines are printed in a symmetrical printing pattern, respectively, on the substrate, and the first bonding wires and the second bonding wires are formed symmetrically, respectively.
摘要翻译：公开了使用对称印刷图案的变压器，其包括：基板; 在基板上以预定距离印刷的多个第一印刷线; 在基板上以预定距离印刷的多个第二印刷线; 连接第一印刷线路的第一接合线; 以及第二接合线，其将第一印刷线和第二印刷线分别以对称的印刷图案印刷在第二印刷线上，并且分别对称地形成第一接合线和第二接合线。

2. 发明申请

US20140327083A1 COMBINATION-TYPE TRANSISTOR AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：组合型晶体管及其制造方法
公开(公告)号：US20140327083A1
公开(公告)日：2014-11-06
申请号：US14361708
申请日：2012-05-15
申请人： Jong Hoon Park , Chang Kun Park
发明人： Jong Hoon Park , Chang Kun Park
IPC分类号： H01L21/8238 , H01L21/8228 , H01L27/06
CPC分类号： H01L21/8238 , H01L21/8228 , H01L27/0623 , H01L27/0705
摘要： Disclosed is a combination-type transistor including a first MOSFET that includes a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; a second MOSFET that includes the gate, a second drain formed on the one side of the gate, and a second source formed on the other side of the gate; a first BJT that is formed such that the first source of the first MOSFET is used as an emitter, the second drain of the second MOSFET is used as a collector, and the substrate is used as a base; and a second BJT that is formed such that the second source of the second MOSFET is used as an emitter, the first drain of the first MOSFET is used as a collector, and the substrate is used as a base.
摘要翻译：公开了一种组合型晶体管，其包括：第一MOSFET，其包括栅极，形成在栅极一侧的第一源极和形成在栅极的另一侧上的第一漏极; 包括栅极的第二MOSFET，形成在栅极一侧的第二漏极和形成在栅极另一侧的第二源极; 第一BJT被形成为使得第一MOSFET的第一源用作发射极，第二MOSFET的第二漏极用作集电极，并且将衬底用作基极; 以及第二BJT，其被形成为使得第二MOSFET的第二源用作发射极，第一MOSFET的第一漏极用作集电极，并且将衬底用作基极。

3. 发明授权

US08717724B2 Diode for electrostatic protection 有权
标题翻译：二极管用于静电保护
公开(公告)号：US08717724B2
公开(公告)日：2014-05-06
申请号：US13881227
申请日：2011-10-13
申请人： Joon Young Park , Jong Hoon Park , Chang Kun Park
发明人： Joon Young Park , Jong Hoon Park , Chang Kun Park
IPC分类号： H02H9/00 , H02H3/22 , H01L29/73 , H01L27/02
CPC分类号： H01L27/0248 , H01L27/0255 , H01L29/861
摘要： Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.
摘要翻译：提供了形成在集成电路（IC）的输入/输出焊盘上的静电放电（ESD）保护二极管，ESD保护二极管包括：构成第一二极管的N型半导体，并连接到焊盘电源电压; 构成第一二极管并连接到信号线的P型半导体; 构成第二二极管并连接到信号线的N型半导体; 构成第二二极管并连接到用于接地的焊盘的P型半导体; 以及通过使第一二极管的N型半导体与第二二极管的P型半导体接触而形成的第三二极管。

4. 发明申请

US20130207224A1 DIODE FOR ELECTROSTATIC PROTECTION 有权
标题翻译：二极管用于静电保护
公开(公告)号：US20130207224A1
公开(公告)日：2013-08-15
申请号：US13881227
申请日：2011-10-13
申请人： Joon Young Park , Jong Hoon Park , Chang Kun Park
发明人： Joon Young Park , Jong Hoon Park , Chang Kun Park
IPC分类号： H01L27/02
CPC分类号： H01L27/0248 , H01L27/0255 , H01L29/861
摘要： Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.
摘要翻译：提供了形成在集成电路（IC）的输入/输出焊盘上的静电放电（ESD）保护二极管，ESD保护二极管包括：构成第一二极管的N型半导体，并连接到焊盘电源电压; 构成第一二极管并连接到信号线的P型半导体; 构成第二二极管并连接到信号线的N型半导体; 构成第二二极管并连接到用于接地的焊盘的P型半导体; 以及通过使第一二极管的N型半导体与第二二极管的P型半导体接触而形成的第三二极管。

5. 发明申请

US20130187745A1 TRANSMISSION-LINE TRANSFORMER IN WHICH SIGNAL EFFICIENCY IS MAXIMISED 有权
标题翻译：传输线变压器的信号效率最大化
公开(公告)号：US20130187745A1
公开(公告)日：2013-07-25
申请号：US13824012
申请日：2011-09-07
申请人： Jong Hoon Park , Chang Kun Park
发明人： Jong Hoon Park , Chang Kun Park
IPC分类号： H01F17/00
CPC分类号： H01P5/12 , H01F17/0006 , H01F19/00 , H01P5/04 , H01P5/10
摘要： Provided is a transmission line transformer having increased signal efficiency. The transmission line transformer is formed on an integrated circuit (IC), wherein a first transmission line disposed in one direction. Second and third transmission lines have same length direction as the first transmission line and are spaced apart from each other in a lateral direction above or below the first transmission line. Accordingly, an area of the first transmission line and areas of the second and third transmission lines, which face each other, are increased, thereby improving a coupling factor. Also, since a secondary transmission line is divided into two regions and uses the second and third transmission lines that have narrower widths than the first transmission line, parasitic capacitance components generated between the first through third transmission lines and a semiconductor substrate may be decreased.
摘要翻译：提供了具有增加的信号效率的传输线变压器。传输线变压器形成在集成电路（IC）上，其中沿一个方向布置的第一传输线。第二传输线和第三传输线具有与第一传输线相同的长度方向，并且在第一传输线上方或下方的横向方向彼此间隔开。因此，第一传输线的面积和彼此相对的第二和第三传输线的面积增加，从而提高耦合系数。此外，由于二次传输线被分成两个区域并且使用具有比第一传输线窄的宽度的第二和第三传输线，所以可以减少在第一至第三传输线和半导体衬底之间产生的寄生电容分量。

6. 发明授权

US08189400B2 Data alignment circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据对准电路
公开(公告)号：US08189400B2
公开(公告)日：2012-05-29
申请号：US12647174
申请日：2009-12-24
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1087
摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.
摘要翻译：用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

7. 发明授权

US08144530B2 Semiconductor memory device and method for generating output enable signal 有权
标题翻译：半导体存储器件和产生输出使能信号的方法
公开(公告)号：US08144530B2
公开(公告)日：2012-03-27
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

8. 发明授权

US08143940B2 Internal supply voltage generating circuit and method for generating internal supply voltage 失效
标题翻译：内部电源电压发生电路及产生内部电源电压的方法
公开(公告)号：US08143940B2
公开(公告)日：2012-03-27
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

9. 发明申请

US20110156772A1 INTERFACE APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND INTERFACING METHOD THEREOF 有权
标题翻译：用于半导体集成电路的接口装置及其接口方法
公开(公告)号：US20110156772A1
公开(公告)日：2011-06-30
申请号：US12650122
申请日：2009-12-30
申请人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K19/0175 , H03K5/1565
摘要： An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.
摘要翻译：半导体集成电路的接口装置及其接口方法响应于由输出块输出的差分信号，将差分信号的VOX控制到目标电平。用于半导体集成电路的接口装置包括：输出块，被配置为输出由内部电路输出的差分信号;检测器，被配置为检测差分信号的定时误差; 以及控制器，被配置为根据检测器的检测结果来控制由内部电路输出的差分信号的定时。

10. 发明授权

US07969214B2 DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit 有权
标题翻译： DLL电路，DLL电路中的更新控制装置和DLL电路的更新方法
公开(公告)号：US07969214B2
公开(公告)日：2011-06-28
申请号：US12493387
申请日：2009-06-29
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.
摘要翻译：延迟锁定环路（DLL）电路包括：相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号。更新控制装置被配置为通过响应于参考时钟信号确定第一逻辑值的数量和相位检测信号的第二逻辑值的数量之间的差异来产生有效间隔信号和更新控制信号。移位寄存器，被配置为当有效间隔信号被使能时响应于更新控制信号来更新授予延迟线的延迟值。

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