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1. 发明申请

US20110128043A1 OUTPUT DRIVER 有权
标题翻译：输出驱动器
公开(公告)号：US20110128043A1
公开(公告)日：2011-06-02
申请号：US12832167
申请日：2010-07-08
申请人： Ic-Su OH , Hyung-Soo Kim , Chang-Kun Park
发明人： Ic-Su OH , Hyung-Soo Kim , Chang-Kun Park
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.
摘要翻译：半导体器件的输出驱动器包括驱动晶体管和体偏置提供单元。驱动晶体管并联耦合，并配置成驱动输出端。身体偏置提供单元被配置为向驱动晶体管提供至少两个级别的相应身体偏置。

2. 发明申请

US20100164568A1 LOW POWER VARIABLE DELAY CIRCUIT 有权
标题翻译：低功耗可变延迟电路
公开(公告)号：US20100164568A1
公开(公告)日：2010-07-01
申请号：US12636901
申请日：2009-12-14
申请人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
发明人： Hae-Rang CHOI , Yong-Ju KIM , Sung-Woo HAN , Hee-Woong SONG , Ic-Su OH , Hyung-Soo KIM , Tae-Jin HWANG , Ji-Wang LEE , Jae-Min JANG , Chang-Kun PARK
IPC分类号： H03L7/00
CPC分类号： G11C19/28
摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
摘要翻译：可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。第一个延迟是M个延迟单位的0或X倍。第三延迟是从0到N个延迟单元中选择的延迟。

3. 发明申请

US20130162314A1 SIGNAL OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：信号输出电路和包括其的半导体器件
公开(公告)号：US20130162314A1
公开(公告)日：2013-06-27
申请号：US13607941
申请日：2012-09-10
申请人： Ic-Su OH
发明人： Ic-Su OH
IPC分类号： H03L7/00
CPC分类号： G11C7/1066 , G11C7/1057 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03K19/0013 , H03K19/018507
摘要： A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.
摘要翻译：信号输出电路包括信号传送单元，其被配置为在第一时钟的激活期间将第一行的信号传送到上拉线，在停用期间将第一行的信号传送到下拉线在第一时钟的去激活期间，将第二线路的信号传送到上拉线路，并且在第二时钟的激活期间将第二线路的信号传送到下拉线路; 以及输出驱动单元，被配置为响应于所述上拉线的信号上拉驱动输出节点并且响应于所述下拉线的信号下拉驱动所述输出节点，其中所述第一时钟和第二时钟具有比去激活周期更长的激活周期。

4. 发明申请

US20090313410A1 BI-DIRECTIONAL MULTI-DROP BUS MEMORY SYSTEM 有权
标题翻译：双向多播总线存储器系统
公开(公告)号：US20090313410A1
公开(公告)日：2009-12-17
申请号：US12477545
申请日：2009-06-03
申请人： Deog-Kyoon JEONG , Suhwan KIM , Woo-Yeol SHIN , Dong-Hyuk LIM , Ic-Su OH
发明人： Deog-Kyoon JEONG , Suhwan KIM , Woo-Yeol SHIN , Dong-Hyuk LIM , Ic-Su OH
IPC分类号： G06F13/00
CPC分类号： G06F13/4086
摘要： A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.
摘要翻译：总线系统包括多个短截线; 多个连接器，每个连接器串联耦合在相应的一个短截线和相应的一个存储器模块之间; 多个第一串联负载，每个第一串联负载串联耦合到对应的一个连接器; 以及多个第二串联负载，每个第二串联负载串联耦合到相应一个短截线的传输线的特征阻抗，其中第一和第二串联负载被确定为在存根

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