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61. 发明授权

US08877606B2 Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation 有权
标题翻译：低成本制造双盒背栅硅绝缘体上晶圆，随后自对准浅沟槽隔离
公开(公告)号：US08877606B2
公开(公告)日：2014-11-04
申请号：US13350889
申请日：2012-01-16
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/76 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L27/1203
摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
摘要翻译：用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及在上绝缘层上形成的半导体层。还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

62. 发明授权

US08754672B2 Voltage conversion and integrated circuits with stacked voltage domains 有权
标题翻译：具有堆叠电压域的电压转换和集成电路
公开(公告)号：US08754672B2
公开(公告)日：2014-06-17
申请号：US13420080
申请日：2012-03-14
申请人： Robert H. Dennard , Brian L. Ji
发明人： Robert H. Dennard , Brian L. Ji
IPC分类号： H03K19/0175
CPC分类号： H03K3/00 , H02M3/07 , H03K3/356139 , H03K19/01806 , H03K19/018521
摘要： A reversible, switched capacitor voltage conversion apparatus includes a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain; and wherein, for both the first and second voltage domains, outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.
摘要翻译：可逆开关电容器电压转换装置包括分阶段地彼此耦合的多个单独单元电池，每个单元电池包括以堆叠配置布置的多组逆变器装置，使得每组逆变器装置在单独的电压域其中相邻电压域中的逆变器装置的输出电容耦合到彼此，使得电容器的第一端子耦合到第一电压域中的第一反相器装置的输出，并且所述电容器的第二端子耦合到在第二电压域中输出第二反相器; 并且其中，对于所述第一和第二电压域两者，所述多个单独单元中的至少一个单元的输出用作所述多个单独单元中的至少另一个的相应输入。

63. 发明授权

US08587063B2 Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels 有权
标题翻译：具有增强的移动通道的混合双盒背栅硅绝缘体上晶圆
公开(公告)号：US08587063B2
公开(公告)日：2013-11-19
申请号：US12613574
申请日：2009-11-06
申请人： Robert H. Dennard , Qiqing C. Ouyang , Jeng-Bang Yau
发明人： Robert H. Dennard , Qiqing C. Ouyang , Jeng-Bang Yau
IPC分类号： H01L29/78
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.
摘要翻译：用于集成电路器件的半导体晶片结构包括块状衬底; 形成在本体基板上的下绝缘层; 形成在下绝缘层上的导电背栅层; 形成在所述背栅层上的上绝缘层; 以及形成在所述上绝缘层上的混合半导体绝缘体层，所述杂化半导体绝缘体层包括具有第一晶体取向的第一部分和具有第二晶体取向的第二部分。

64. 发明授权

US08586426B2 Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box 失效
标题翻译：用超薄SOI和超薄盒形成SOI器件隔离结构的方法
公开(公告)号：US08586426B2
公开(公告)日：2013-11-19
申请号：US13566568
申请日：2012-08-03
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

65. 发明授权

US08473762B2 Power delivery in a heterogeneous 3-D stacked apparatus 有权
标题翻译：在异种3-D堆叠设备中的功率输送
公开(公告)号：US08473762B2
公开(公告)日：2013-06-25
申请号：US13552091
申请日：2012-07-18
申请人： Robert H. Dennard , Eren Kursun
发明人： Robert H. Dennard , Eren Kursun
IPC分类号： G06F1/00 , G06F1/26 , H01L23/02 , H01L23/52 , H02J1/10 , B23K11/24
CPC分类号： H01L25/18 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , Y10T307/50
摘要： A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
摘要翻译：提供了一种不均匀的三维（3-D）层叠装置，其包括以堆叠配置布置的多个层，其中下层被配置为接收板级电压，以及堆叠在下层上方的一个或多个上层。异质三维层叠装置还包括每层多个瓦片，其中每个瓦片被设计成接收单独调节的电压。异质三层堆叠装置还包括在一个或多个上层中的至少一个层，其中电压转换器提供从板级电压转换的单独调节的电压。

66. 发明授权

US08395438B2 Switched capacitor voltage converters 有权
标题翻译：开关电容电压转换器
公开(公告)号：US08395438B2
公开(公告)日：2013-03-12
申请号：US13532986
申请日：2012-06-26
申请人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
发明人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , H02M3/07
摘要： An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
摘要翻译：集成电路的片上电压转换装置包括第一电容器; 第一NFET器件被配置为选择性地将第一电容器的第一电极耦合到第一电压域的低侧电压轨; 第一PFET器件，被配置为选择性地将第一电容器的第一电极耦合到第一电压域的高侧电压轨; 第二NFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的低侧电压轨，其中第二电压域的低侧电压轨对应于第一电压域的高侧电压轨 ; 以及第二PFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的高侧电压轨。

67. 发明申请

US20130005095A1 ETSOI CMOS With Back Gates 有权
标题翻译： ETSOI CMOS后盖
公开(公告)号：US20130005095A1
公开(公告)日：2013-01-03
申请号：US13611656
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203
摘要： A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
摘要翻译：制造结构的方法包括提供绝缘体上硅晶片，通过半导体层和绝缘层注入具有与衬底顶表面相邻的第一导电类型的功能区域; 在功能区域内通过半导体层和绝缘层注入具有第二类导电性的电浮置背栅区; 在半导体层中形成隔离区; 形成第一和第二晶体管器件以在半导体层上具有相同类型的导电性，使得晶体管器件中的一个覆盖在注入的背栅极区域上，另一个晶体管器件仅覆盖不重叠的功能区域的下面的顶部表面通过植入的背栅区; 以及向所述功能区域提供电接触以施加偏置电压。

68. 发明申请

US20120299105A1 ETSOI CMOS with Back Gates 有权
标题翻译：带后盖的ETSOI CMOS
公开(公告)号：US20120299105A1
公开(公告)日：2012-11-29
申请号：US13114410
申请日：2011-05-24
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203
摘要： A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
摘要翻译：结构具有具有第一类型的导电性的功能区域和顶表面。功能区域连接到偏置触点。该结构还包括绝缘层; 半导体层和具有相同类型导电性的第一和第二晶体管器件设置在半导体层上。所述结构还包括与所述顶表面相邻并且位于所述晶体管器件之一下方的第一后栅极区域，所述第一背栅极区域具有第二类型的导电性; 以及与顶表面相邻并且位于另一个晶体管器件下方的第二背栅极区域，第二背栅极区域具有第一类型的导电性。第一晶体管器件具有第一特征阈值电压，并且第二晶体管器件具有不同于第一特征阈值电压的第二特征阈值电压。

69. 发明授权

US08236661B2 Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage 有权
标题翻译：自对准井注入，用于改善短沟道效应控制，寄生电容和结漏电
公开(公告)号：US08236661B2
公开(公告)日：2012-08-07
申请号：US12568287
申请日：2009-09-28
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.
摘要翻译：形成用于晶体管的自对准阱注入的方法包括在衬底上形成图案化栅极结构，该衬底包括栅极导体，栅极电介质层和侧壁间隔物，所述衬底包括在栅极介电层下面的未掺杂的半导体层，以及未掺杂的半导体层下面的掺杂半导体层; 去除未图示的栅极结构保护的未掺杂半导体层和掺杂半导体层的部分，其中在图案化栅极结构下面的未掺杂半导体层的剩余部分限定晶体管沟道，并且掺杂半导体层的图案化下面的掺杂半导体层的剩余部分栅极结构定义了自对准阱植入物; 以及在对应于未掺杂半导体层和掺杂半导体层的去除部分的位置处生长新的半导体层，新的半导体层对应于晶体管的源极和漏极区域。

70. 发明授权

US08227865B2 Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer 有权
标题翻译：低成本制造双盒背栅硅绝缘体晶片，在背栅层中内置浅沟槽隔离
公开(公告)号：US08227865B2
公开(公告)日：2012-07-24
申请号：US12751302
申请日：2010-03-31
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen She , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen She , Jeng-Bang Yau
IPC分类号： H01L27/01
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/78648
摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.
摘要翻译：用于制造集成电路器件的半导体晶片结构包括体基片; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在所述下绝缘层上的导电层，所述导电层还具有形成在其中的一个或多个浅沟槽隔离（STI）区域; 形成在所述导电层和所述一个或多个STI区域上的蚀刻停止层; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了随后的有源面积电平STI方案，结合半导体层上的前栅极形成。

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