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1. 发明授权

US08716807B2 Fabrication of devices having different interfacial oxide thickness via lateral oxidation 有权
标题翻译：通过侧面氧化制备具有不同界面氧化物厚度的器件
公开(公告)号：US08716807B2
公开(公告)日：2014-05-06
申请号：US13571521
申请日：2012-08-10
申请人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
发明人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
IPC分类号： H01L21/70
CPC分类号： H01L21/823468 , H01L21/28176 , H01L21/28247 , H01L21/823462 , H01L21/823857 , H01L21/823864 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/78
摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.
摘要翻译：半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

2. 发明授权

US08658530B2 Method of fabricating an epitaxial Ni silicide film 有权
标题翻译：制造外延Ni硅化物膜的方法
公开(公告)号：US08658530B2
公开(公告)日：2014-02-25
申请号：US13612240
申请日：2012-09-12
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L21/4763 , H01L21/477 , H01L21/36
CPC分类号： H01L29/7839 , H01L21/28052 , H01L21/28537 , H01L29/47 , H01L29/665 , H01L29/66643 , H01L29/66772 , H01L29/78618
摘要： An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.
摘要翻译：提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

3. 发明授权

US08536012B2 Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases 有权
标题翻译：具有连接内在和外在基极的连接区域的双极结晶体管
公开(公告)号：US08536012B2
公开(公告)日：2013-09-17
申请号：US13177146
申请日：2011-07-06
申请人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
发明人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/02
CPC分类号： H01L29/73 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/107 , H01L29/66272 , H01L29/7322
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
摘要翻译：用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。发射极开口延伸穿过外部基极和电介质层。电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

4. 发明授权

US08482084B2 SOI schottky source/drain device structure to control encroachment and delamination of silicide 失效
标题翻译： SOI肖特基源/漏极器件结构，以控制硅化物的侵蚀和分层
公开(公告)号：US08482084B2
公开(公告)日：2013-07-09
申请号：US12726789
申请日：2010-03-18
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L29/76 , H01L31/00
CPC分类号： H01L29/78654 , H01L29/7839
摘要： A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.
摘要翻译：提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。栅极结构存在于半导体材料层上。在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。凸起的源极和漏极区域是肖特基源极和漏极区域。在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和漏区和电介质层。

5. 发明授权

US08420469B2 Schottky FET fabricated with gate last process 失效
标题翻译：用最后一道工艺制造的肖特基FET
公开(公告)号：US08420469B2
公开(公告)日：2013-04-16
申请号：US12834428
申请日：2010-07-12
申请人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
发明人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
IPC分类号： H01L21/338
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66621
摘要： A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.
摘要翻译：一种形成场效应晶体管（FET）的方法包括在绝缘体上半导体衬底的顶部半导体层上形成一个虚拟栅极; 在顶部半导体层中形成源极和漏极区域，其中源极和漏极区域位于虚拟栅极的任一侧的顶部半导体层中; 在与所述虚拟栅极相邻的所述源极和漏极区域上形成支撑材料; 去除所述伪栅极以形成栅极开口，其中所述顶部半导体层的沟道区域通过所述栅极开口暴露; 通过栅极开口来稀薄顶部半导体层的沟道区域; 以及在所述变薄的通道区域上的所述栅极开口中形成栅极间隔物和栅极。

6. 发明申请

US20120289018A1 SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译： SOI SiGe-BASE横向双极晶体管晶体管
公开(公告)号：US20120289018A1
公开(公告)日：2012-11-15
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

7. 发明申请

US20110260252A1 USE OF EPITAXIAL NI SILICIDE 有权
标题翻译：外用矽硅胶的使用
公开(公告)号：US20110260252A1
公开(公告)日：2011-10-27
申请号：US12766468
申请日：2010-04-23
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L27/12 , H01L21/3205 , H01L29/786 , H01L23/532 , H01L29/78
CPC分类号： H01L29/7839 , H01L21/28052 , H01L21/28537 , H01L29/47 , H01L29/665 , H01L29/66643 , H01L29/66772 , H01L29/78618
摘要： An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.
摘要翻译：提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

8. 发明申请

US20110227156A1 SOI Schottky Source/Drain Device Structure to Control Encroachment and Delamination of Silicide 失效
标题翻译： SOI肖特基源/排水装置结构，以控制硅化物的侵蚀和分层
公开(公告)号：US20110227156A1
公开(公告)日：2011-09-22
申请号：US12726789
申请日：2010-03-18
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L27/12
CPC分类号： H01L29/78654 , H01L29/7839
摘要： A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.
摘要翻译：提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。栅极结构存在于半导体材料层上。在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。凸起的源极和漏极区域是肖特基源极和漏极区域。在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和漏区和电介质层。

9. 发明授权

US07888745B2 Bipolar transistor with dual shallow trench isolation and low base resistance 有权
标题翻译：具有双浅沟槽隔离和低基极电阻的双极晶体管
公开(公告)号：US07888745B2
公开(公告)日：2011-02-15
申请号：US11425550
申请日：2006-06-21
申请人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
发明人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
IPC分类号： H01L29/72
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译：提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。该对相邻的第一STI区域限定衬底中的有源区域。该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。根据本发明，凸起的外在基部具有对基底层的一部分的开口。发射器位于开口中并在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。第二STI区域具有倾斜的内侧壁表面。在一些实施方案中，碱是完全单晶的。

10. 发明申请

US20110033952A1 Sensor for Biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US20110033952A1
公开(公告)日：2011-02-10
申请号：US12537063
申请日：2009-08-06
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/543 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.
摘要翻译：用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动当生物分子与抗体结合时，在源区和漏区之间变化。

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