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61. 发明申请

US20050152190A1 Semiconductor memory device capable of testing memory cells at high speed 有权
标题翻译：能够高速测试存储单元的半导体存储器件
公开(公告)号：US20050152190A1
公开(公告)日：2005-07-14
申请号：US11008270
申请日：2004-12-10
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G01R31/28 , G01R31/3183 , G11C29/12 , G11C29/36 , G11C5/00
CPC分类号： G11C29/36 , G11C2029/3602
摘要： A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.
摘要翻译：半导体存储器件包括存储器核，数据控制电路，标志寄存器，数据寄存器和计算电路。存储器核具有用于存储数据的多个存储单元。数据控制电路与时钟信号同步地向存储器单元写入和读出第一测试数据。标志寄存器存储多个标志数据项。数据寄存器存储对应于命令输入的第二测试数据输入。计算电路在每个周期执行存储在数据寄存器中的第二测试数据和存储在标志寄存器中的每个标志数据项的计算，从而生成第一测试数据，直到第n（n是时钟信号的正整数）周期。第一测试数据由数据控制电路写入存储单元。

62. 发明授权

US06697292B1 Semiconductor memory device capable of changing the selection order of sense amplifiers 失效
标题翻译：能够改变读出放大器选择顺序的半导体存储器件
公开(公告)号：US06697292B1
公开(公告)日：2004-02-24
申请号：US10462695
申请日：2003-06-17
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C2900
CPC分类号： G11C7/1048 , G11C11/4096 , G11C2029/1204 , G11C2207/002
摘要： A semiconductor memory device comprising a plurality of memory cells to store data, k data input/output lines (k=a natural number), a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells, a column selection gate which selects one sense amplifier among the n sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line, a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . , n) among the n sense amplifiers, and a switching circuit which changes the order of selecting the m sense amplifiers by the selector circuit.
摘要翻译：一种半导体存储器件，包括用于存储数据的多个存储器单元，k个数据输入/输出线（k =自然数），对于k个数据以n个数（n =自然数）提供的多个读出放大器输入/输出线，并且对多个存储单元执行读和写单元数据;列选择门，其选择n个读出放大器中的一个读出放大器，并将所选择的读出放大器连接到对应的数据输入/输出线; 选择器电路，其控制列选择门，并且顺序地选择n个读出放大器中的m个读出放大器（m = 1,2，...，n），以及切换电路，其改变由m个读出放大器选择m个读出放大器的顺序选择器电路。

63. 发明授权

US06259636B1 Semiconductor memory device having redundancy circuit for relieving faulty memory cells 失效
标题翻译：具有用于缓解故障存储单元的冗余电路的半导体存储器件
公开(公告)号：US06259636B1
公开(公告)日：2001-07-10
申请号：US09257505
申请日：1999-02-25
申请人： Ryo Fukuda , Toshimasa Namekawa
发明人： Ryo Fukuda , Toshimasa Namekawa
IPC分类号： G11C2900
CPC分类号： G11C29/808 , G11C29/812
摘要： In a semiconductor memory device having a redundant cell array, a replacement control circuit stores in advance a faulty address in an address space assigned to the memory cell array and information for specifying the dimension of the faulty address, compares each of external addresses XA and YA with the stored faulty address, and detects their coincidence. When the external address coincides with the faulty address, a redundant row or a redundant column constituting the redundant cell array is selected and replaced with the faulty cell, on the basis of the information representing the dimension of the faulty address. By this operation, the faulty cell on the memory cell array can be flexibly relieved, and the flexibility of redundancy can be improved.
摘要翻译：在具有冗余单元阵列的半导体存储器件中，替换控制电路预先存储分配给存储单元阵列的地址空间中的故障地址和用于指定故障地址的维度的信息，比较每个外部地址XA和YA 与存储的故障地址，并检测到它们的巧合。当外部地址与故障地址一致时，根据表示故障地址的维度的信息，选择构成冗余单元阵列的冗余行或冗余列，并将其替换为故障单元。通过这种操作，可以灵活地解除存储单元阵列上的故障单元，并且可以提高冗余的灵活性。

64. 发明授权

US5717625A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5717625A
公开(公告)日：1998-02-10
申请号：US784963
申请日：1997-01-16
申请人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
发明人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
IPC分类号： G11C8/08 , G11C11/404 , G11C15/00
CPC分类号： G11C8/08 , G11C11/4045
摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.
摘要翻译：在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

65. 发明授权

US5684746A Semiconductor memory device in which a failed memory cell is placed with another memory cell 失效
标题翻译：半导体存储器件，其中故障存储器单元被另一存储单元替代
公开(公告)号：US5684746A
公开(公告)日：1997-11-04
申请号：US567688
申请日：1995-12-05
申请人： Yukihito Oowaki , Ryo Fukuda
发明人： Yukihito Oowaki , Ryo Fukuda
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/24 , H01L21/82 , H01L27/10 , G11C7/00
CPC分类号： G11C29/76 , G11C29/24
摘要： A semiconductor memory device including a memory cell array having memory cells arranged in XY directions, means for storing at least X addresses of failure bit memory cells among memory cells defined by an X address and a Y address in the memory cell array, and address means for generating an address Xe+m (m=positive or negative integer), serving as an internal address, when X address Xe corresponding to the failure bit address is inputted from an external section.
摘要翻译：一种半导体存储器件，包括具有以XY方向布置的存储单元的存储单元阵列，用于在存储单元阵列中由X地址和Y地址定义的存储单元中存储故障位存储单元的至少X个地址的装置，以及地址单元用于当从外部输入与故障位地址对应的X地址Xe时，产生用作内部地址的地址Xe + m（m =正或负整数）。

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