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61. 发明授权

US09612272B2 Testing memory devices with parallel processing operations 有权
公开(公告)号：US09612272B2
公开(公告)日：2017-04-04
申请号：US14191289
申请日：2014-02-26
申请人： Advantest Corporation
发明人： Xinguo Zhang , Michael Jones , Ken Hanh Duc Lai , Edmundo De La Puente , Alan S. Krech, Jr.
IPC分类号： G01R31/26 , G11C29/56
CPC分类号： G01R31/26 , G11C29/56008
摘要： An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

62. 发明授权

US09606170B2 Handler apparatus that conveys a device under test to a test socket and test apparatus that comprises the handler apparatus 有权
公开(公告)号：US09606170B2
公开(公告)日：2017-03-28
申请号：US14472394
申请日：2014-08-29
申请人： ADVANTEST CORPORATION
发明人： Tsuyoshi Yamashita , Mitsunori Aizawa , Hiromitsu Horino , Yuya Yamada , Masataka Onozawa
IPC分类号： G01R31/28 , G01C11/00 , G01R1/04
CPC分类号： G01R31/2891 , G01C11/00 , G01R1/0441 , G01R31/2893
摘要： Provided is a handler apparatus that conveys a device under test to a test socket, including: a socket fitting unit which the test socket fits, prior to fitting of a device holder holding the device under test to the test socket; a test-socket position detecting section that detects a relative position of the socket fitting unit with respect to the test socket in a state in which the socket fitting unit fits the test socket; an actuator that adjusts a position of the device under test on the device holder, based on the detected relative position of the socket fitting unit; and a conveyer that conveys the device holder in which the position of the device under test has been adjusted, to fit the test socket.

63. 发明申请

US20170082668A1 MEASURING APPARATUS, MEASURING METHOD, AND RECORDING MEDIUM 审中-公开
公开(公告)号：US20170082668A1
公开(公告)日：2017-03-23
申请号：US15231997
申请日：2016-08-09
申请人： ADVANTEST CORPORATION
发明人： Tsuyoshi ATAKA , Masaichi HASHIMOTO
IPC分类号： G01R23/02
CPC分类号： G01R23/02 , G01R23/04 , G01R27/32
摘要： A measuring apparatus according to the present invention includes a response signal measuring section, an input frequency domain conversion section, a response frequency domain conversion section, and a frequency characteristic acquisition section. The response signal measuring section measures a response signal within a time domain, the response signal being acquired by applying a pulse having a width of not less than one femtosecond nor more than 1000 femtoseconds to an object to be measured. The input frequency domain conversion section converts the pulse into a frequency domain. The response frequency domain conversion section converts a measurement result from the response signal measuring section into a frequency domain. The frequency characteristic acquisition section acquires a frequency characteristic of the object to be measured, from a conversion result provided from the input frequency domain conversion section and a conversion result provided from the response frequency domain conversion section.

64. 发明授权

US09575726B2 Bit sequence generator and apparatus for calculating a sub-rate transition matrix and a sub-rate initial state for a state machine of a plurality of state machines 有权
标题翻译：用于计算多个状态机的状态机的子速率转换矩阵和子速率初始状态的位序发生器和装置
公开(公告)号：US09575726B2
公开(公告)日：2017-02-21
申请号：US13814234
申请日：2010-08-03
申请人： Jochen Rivoir
发明人： Jochen Rivoir
IPC分类号： G06F7/58 , H03K3/64 , H03K3/84
CPC分类号： G06F7/58 , G06F7/584 , G06F2207/582 , H03K3/64 , H03K3/84
摘要： A bit sequence generator for generating a bit sequence defined by a generating function and an initial state of the generating function comprising a plurality of state machines and a multiplexer. Each state machine of the plurality of state machines generates a time-interleaved bit sequence, wherein a state machine generates a bit of the time-interleaved bit sequence for a current time step based on at least one bit generated by the state machine for a preceding time step, the generating function of the bit sequence to be generated, and the initial state of the generating function and independent from a time-interleaved bit sequence generated by another state machine of the plurality of state machines. Further, a multiplexer selects successively one bit from each generated time-interleaved bit sequence in a repetitive manner to obtain the bit sequence defined by the generating function and the initial state of the generating function.
摘要翻译：一种用于生成由生成函数定义的比特序列和包括多个状态机和多路复用器的生成函数的初始状态的比特序列生成器。多个状态机的每个状态机产生时间交织的比特序列，其中状态机基于状态机为前一个生成的至少一个比特生成当前时间步长的时间交织比特序列的比特时间步长，要生成的比特序列的生成函数，以及生成函数的初始状态，并且与多个状态机的另一状态机生成的时间交织的比特序列无关。此外，复用器以重复的方式从每个生成的时间交织比特序列连续地选择一个比特，以获得由生成函数定义的比特序列和生成函数的初始状态。

65. 发明授权

US09554291B2 Generation of RF stimulus signal using DC modulating signal 有权
标题翻译：使用直流调制信号产生RF激励信号
公开(公告)号：US09554291B2
公开(公告)日：2017-01-24
申请号：US14614327
申请日：2015-02-04
申请人： Advantest Corporation
发明人： Jason Smith
IPC分类号： H04W24/06
CPC分类号： H04W24/06
摘要： Systems and methods of generating an RF stimulus signal with different power levels for IC testing. A DC modulating signal is used to power modulate a radio frequency (RF) carrier signal and thereby generate an RF stimulus signal at varying power levels. The DC modulating signal includes a sequence of DC waveforms at different voltage levels. A DC voltage transition in the modulating signal instantaneously triggers the transition of an output power in the RF stimulus signal. Reference waveforms that can cause a known response pattern in a DUT may be added at the beginning of the modulating signal for data calibration purposes.
摘要翻译：生成具有不同功率电平的RF激励信号用于IC测试的系统和方法。 DC调制信号用于对射频（RF）载波信号进行功率调制，从而以变化的功率电平产生RF激励信号。 DC调制信号包括不同电压电平的一系列DC波形。调制信号中的直流电压转换瞬间触发RF激励信号中的输出功率的转变。可以在调制信号的开始处添加可能导致DUT中已知响应模式的参考波形，用于数据校准目的。

66. 发明授权

US09417181B2 Dynamic measurement of density using terahertz radiation with real-time thickness measurement for process control 有权
标题翻译：使用太赫兹辐射进行动态测量，实时测量过程控制
公开(公告)号：US09417181B2
公开(公告)日：2016-08-16
申请号：US14273252
申请日：2014-05-08
申请人： Advantest Corporation
发明人： Edward King , David Heaps , Mark Sullivan
IPC分类号： G01N21/3563 , G01N21/3581 , G01N21/3586 , G01B11/06 , G01N21/85 , G01N21/89 , G01N21/95 , G01N9/24
CPC分类号： G01N21/3586 , G01B11/0691 , G01N9/24 , G01N21/3563 , G01N21/3581 , G01N21/85 , G01N21/8901 , G01N21/8914 , G01N21/9508 , G01N2021/3572 , G01N2201/06113
摘要： A method of determining a density of a roller compacted ribbon is disclosed. The method comprises compacting dry pharmaceutical powder between press rollers of a roller compactor to produce a compact ribbon. The method also comprises determining a thickness at a point on the compact ribbon in a non-invasive manner after it has rolled out from in between the press rollers. Further, the method comprises passing the compact ribbon through a gap in between the terahertz emitter and the terahertz detector. Next, the method comprises determining a refractive index at the point on the compact ribbon using a measurement value from the terahertz emitter and the terahertz detector and a measured value for the thickness at the point. Finally, the method comprises computing a density of the compact ribbon at the point using a value of the refractive index.
摘要翻译：公开了一种确定辊压紧带的密度的方法。该方法包括在辊式压实机的压辊之间压制干燥的药物粉末，以产生紧凑的带状物。该方法还包括在压榨辊之间从其压出辊之间以非侵入方式确定紧密带上的一个点处的厚度。此外，该方法包括使紧凑带通过太赫兹发射极和太赫兹检测器之间的间隙。接下来，该方法包括使用来自太赫兹发射器和太赫兹检测器的测量值以及在该点处的厚度的测量值来确定紧凑型带上的点处的折射率。最后，该方法包括使用折射率的值计算该点处的紧密带的密度。

67. 发明授权

US09329215B2 Impedance measurement apparatus 有权
标题翻译：阻抗测量装置
公开(公告)号：US09329215B2
公开(公告)日：2016-05-03
申请号：US14319914
申请日：2014-06-30
申请人： ADVANTEST CORPORATION
发明人： Yuki Endo , Yasuo Furukawa , Tomoaki Ueda
IPC分类号： G01R27/02
CPC分类号： G01R27/02
摘要： A measurement auxiliary circuit is configured to form a resonance circuit together with a detection target. An ATAC is coupled with the resonance circuit. A signal generator applies an AC probe signal VS to the resonance circuit. After the impedance measurement apparatus enters a stable state, an impedance detection unit measures a voltage at at least one node and/or a current that flows through at least one current path. The impedance detection unit detects the impedance of the detection target based on the measurement value.
摘要翻译：测量辅助电路被配置为与检测目标一起形成谐振电路。 ATAC与谐振电路耦合。信号发生器将AC探针信号VS施加到谐振电路。在阻抗测量装置进入稳定状态之后，阻抗检测单元测量至少一个节点处的电压和/或流经至少一个电流路径的电流。阻抗检测单元基于测量值来检测检测对象物的阻抗。

68. 发明授权

US09317351B2 System, methods and apparatus using virtual appliances in a semiconductor test environment 有权
标题翻译：在半导体测试环境中使用虚拟设备的系统，方法和设备
公开(公告)号：US09317351B2
公开(公告)日：2016-04-19
申请号：US13821559
申请日：2010-09-07
申请人： Klaus-Dieter Hilliges , Jia-Wei Lin , Duncan Gurley , Jim-my Jin , Eric Vokerink
发明人： Klaus-Dieter Hilliges , Jia-Wei Lin , Duncan Gurley , Jim-my Jin , Eric Vokerink
IPC分类号： G06F11/00 , G06F11/07 , G06F11/22 , G06F11/30 , G01R31/28 , G01R31/319 , G06F11/26 , G06F9/455
CPC分类号： G06F11/0712 , G01R31/2834 , G01R31/31907 , G05B19/41875 , G05B2219/45031 , G06F9/45533 , G06F11/2205 , G06F11/2273 , G06F11/261 , G06F11/301
摘要： In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
摘要翻译：在一个实施例中，半导体测试控制系统包括具有多个硬件资源的计算机系统; 安装在计算机系统上的管理程序; 以及安装在计算机系统上的测试台控制器。管理程序虚拟化硬件资源，并且向至少一个虚拟设备中的每一个提供对相应虚拟硬件资源组的访问。硬件资源的每个虚拟集合使其相应的虚拟设备与半导体测试系统的至少第一方面进行控制通信，从而使得相应的虚拟设备能够测试相应类型的半导体器件。测试台控制器正在控制与i）半导体测试系统的至少第二方面的通信，以及ii）至少一个虚拟设备中的每一个。

69. 发明授权

US09300309B2 Apparatus and method for source synchronous testing of signal converters 有权
标题翻译：信号转换器源同步测试装置及方法
公开(公告)号：US09300309B2
公开(公告)日：2016-03-29
申请号：US13640287
申请日：2010-04-09
申请人： Bernd Laquai
发明人： Bernd Laquai
IPC分类号： H03M1/10 , H03M1/06 , H03M1/12
CPC分类号： H03M1/0624 , H03M1/1071 , H03M1/12
摘要： An automatic tester, comprising a first signal converter, a first signal path, and a second signal path. The first signal converter is operable to convert, using a conversion clock signal, a signal from a digital signal domain to an analog signal domain to acquire an analog stimulus signal. The first signal path is operable to forward the analog stimulus signal from the first signal converter to a second signal converter operable to convert the analog stimulus signal back from the analog signal domain to the digital signal domain. The second signal path is operable to forward one of the conversion clock signal and a signal derived thereof from the first signal converter to the second signal converter. A difference between a propagation delay of an analog stimulus signal in response to a clock cycle of the conversion clock signal via the first signal path and a propagation delay of the conversion clock signal of the clock cycle via the second signal path is within a predetermined tolerance range.
摘要翻译：一种自动测试器，包括第一信号转换器，第一信号路径和第二信号路径。第一信号转换器可操作以使用转换时钟信号将来自数字信号域的信号转换为模拟信号域以获取模拟刺激信号。第一信号路径可操作以将模拟刺激信号从第一信号转换器转发到可操作以将模拟刺激信号从模拟信号域转换回数字信号域的第二信号转换器。第二信号路径可操作以将转换时钟信号和从其导出的信号中的一个从第一信号转换器转发到第二信号转换器。响应于经由第一信号路径的转换时钟信号的时钟周期的模拟刺激信号的传播延迟和经由第二信号路径的时钟周期的转换时钟信号的传播延迟之间的差异在预定公差内范围。

70. 发明授权

US09262376B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US09262376B2
公开(公告)日：2016-02-16
申请号：US13734211
申请日：2013-01-04
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： H04B3/46 , G06F17/00 , G01R31/319 , G01R31/26 , G01R31/317
CPC分类号： G06F17/00 , G01R31/2601 , G01R31/31726 , G01R31/31908
摘要： A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.
摘要翻译：同步模式生成单元生成已经内置于DUT中的时钟恢复单元所需的同步模式，以保持与外部电路的链接。门信号产生单元产生门限信号，该信号在向DUT提供矢量模式的周期内被断言。在第一模式中，模式选择单元被配置为使得在门信号被断言的时段期间输出矢量模式，并且在门信号被否定的时段期间输出固定的输出电平。在第二模式中，模式选择单元被配置为使得在门信号被断言的时段期间输出矢量模式，并且在门信号被否定的时段期间输出该同步模式。

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