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1. 发明申请

US20180323794A1 METHOD FOR SYNCHRONISING DATA CONVERTERS BY MEANS OF A SIGNAL TRANSMITTED FROM ONE TO THE NEXT 审中-公开
公开(公告)号：US20180323794A1
公开(公告)日：2018-11-08
申请号：US15774455
申请日：2016-11-04
申请人： Teledyne e2v Semiconductors SAS
发明人： Etienne BOUIN , Rémi LAUBE , Jérôme LIGOZAT , Marc STACKLER
IPC分类号： H03M1/06
CPC分类号： H03M1/0624 , H03K5/1534 , H03K2005/00267 , H03M1/1215
摘要： In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

2. 发明申请

US20180234103A1 DEVICE AND METHOD FOR REQUESTING AN ANALOG-TO-DIGITAL CONVERSION 审中-公开
公开(公告)号：US20180234103A1
公开(公告)日：2018-08-16
申请号：US15895453
申请日：2018-02-13
申请人： Infineon Technologies AG
发明人： Jens Barrenscheen , Peter Bogner , Juergen Schaefer
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H02M3/33546 , H02P27/06 , H03M1/0624 , H03M1/122
摘要： An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

3. 发明申请

US20180167080A1 Phase Adjustment for Interleaved Analog to Digital Converters 审中-公开
公开(公告)号：US20180167080A1
公开(公告)日：2018-06-14
申请号：US15823355
申请日：2017-11-27
申请人： Rambus Inc.
发明人： Kenneth C. Dyer
IPC分类号： H03M1/12 , H03M1/06 , H03M1/08
CPC分类号： H03M1/1255 , H03M1/0624 , H03M1/0673 , H03M1/0836 , H03M1/1028 , H03M1/1057 , H03M1/1215
摘要： An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

4. 发明授权

US09980683B2 Analog/digital conversion system, X-ray CT apparatus, and medical image imaging apparatus 有权
公开(公告)号：US09980683B2
公开(公告)日：2018-05-29
申请号：US15504259
申请日：2015-08-05
申请人： Hitachi, Ltd.
发明人： Masafumi Onouchi
IPC分类号： H03M1/06 , A61B6/03 , H03M1/12
CPC分类号： A61B6/035 , A61B6/03 , H03M1/0624 , H03M1/1245 , H03M1/1265
摘要： In order to provide a highly precise analog/digital conversion system in which an output error of an AD converter is small, sampling is performed at a certain sampling period S from the start time of a measurement period TL to the (N−1)-th sampling when the measurement period TL does not correspond to the sampling period S multiplied by the number of samplings N, the N-th sampling is performed at a timing when a time interval between the (N−1)-th sampling and the N-th sampling is equal to the sampling period S multiplied by a predetermined coefficient k, and the k value is set to a non-integer optimum value evaluated in advance in accordance with the N value in order to minimize an error of the detection value of the AD converter.

5. 发明授权

US09800228B2 Delay line system, high frequency sampler, analog-to-digital converter and oscilloscope 有权
公开(公告)号：US09800228B2
公开(公告)日：2017-10-24
申请号：US14859899
申请日：2015-09-21
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Ols Hidri
IPC分类号： H03H11/26 , G01R13/02 , H03K5/159 , H03M1/12
CPC分类号： H03H11/265 , G01R13/0272 , H03K5/159 , H03M1/0624 , H03M1/1215 , H03M1/124
摘要： A delay line device is provided for a high frequency sampler for high frequency signal transmission, or for an oscilloscope for measuring high frequency signals. The delay line device includes two distributed tapped transmission delay lines. Each of the delay lines includes two terminals. An analog input signal is applied to a first terminal of the first delay line, and a clock signal is applied to a first terminal of the second delay line. The delay lines are configured such that the analog input signal propagates through the first delay line in an opposite direction as compared to the propagation of the clock signal through the second delay line.

6. 发明申请

US20170257109A1 Apparatus for Data Converter with Internal Trigger Circuitry and Associated Methods 审中-公开
公开(公告)号：US20170257109A1
公开(公告)日：2017-09-07
申请号：US15427014
申请日：2017-02-07
申请人： Silicon Laboratories Inc.
发明人： Wajid Hassan Minhass , Oeivind A. G. Loe
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/12 , H03M1/002 , H03M1/0624
摘要： An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

7. 发明申请

US20170118009A1 PRECISION CLOCK ENABLED TIME-INTERLEAVED DATA CONVERSION 有权
公开(公告)号：US20170118009A1
公开(公告)日：2017-04-27
申请号：US14921157
申请日：2015-10-23
申请人： Raytheon Company
发明人： Steven R. Wilkinson , Bishara Shamee
IPC分类号： H04L7/00 , H04L7/08
CPC分类号： G01S3/00 , G02F7/00 , H01S3/1303 , H01S3/1305 , H01S3/1307 , H03K3/42 , H03K5/13 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H03M1/662
摘要： An apparatus comprises a photonic oscillator circuit configured to generate optical signals that are separated by a uniform delay; radio frequency (RF) generating circuitry configured to receive the optical signals and produce a series of reference clock signals having a same clock signal frequency, wherein each reference clock signal in the series includes a uniform delay from a previous clock signal in the series; and a plurality of analog-to-digital converter (ADC) circuits, wherein an ADC circuit includes a signal input to directly receive an RF input signal that is continuous in time and amplitude, and a clock input to receive a reference clock signal of the repeating series of reference clock signals, wherein the ADC circuits are configured to sample a RF input signal at the frequency of the reference clock signal with the uniform delay to sample interleaved digital values representing the RF signal.

8. 发明授权

US09553600B1 Skew detection and correction in time-interleaved analog-to-digital converters 有权
标题翻译：时间交错模数转换器中的偏斜检测和校正
公开(公告)号：US09553600B1
公开(公告)日：2017-01-24
申请号：US15187161
申请日：2016-06-20
申请人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
发明人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
IPC分类号： H03M1/06 , H03M1/12 , H03M1/00 , H04L7/00
CPC分类号： H03M1/0624 , G06F1/10 , H03M1/00 , H03M1/12 , H03M1/1215 , H03M1/1225 , H04L7/0008
摘要： The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.
摘要翻译：本公开提供了一种用于校正时间交织的模数转换器中的时钟偏移的系统，电路和方法。沿相应的通道接收至少两个时钟信号。通过对通道应用一个或多个第一调整因子直到第一时钟信号的边沿与参考信号的转换点对准来考虑承载第一时钟信号的第一通道的延迟。第一个时钟信号被交换到第二个信道，反之亦然。将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道的偏斜，以及一个或多个第二信道基于确定的第二通道的倾斜度，将调整因子应用于第二通道。

9. 发明授权

US09515626B2 Digital/analogue conversion 有权
标题翻译：数字/模拟转换
公开(公告)号：US09515626B2
公开(公告)日：2016-12-06
申请号：US14436648
申请日：2013-10-10
申请人： Cirrus Logic International Semiconductor Limited
发明人： John Paul Lesso
IPC分类号： H03M1/00 , H03G3/00 , H03M1/06 , H03M1/66 , H03M1/08 , H03M1/70
CPC分类号： H03G3/001 , H03M1/0624 , H03M1/0626 , H03M1/0863 , H03M1/66 , H03M1/70
摘要： The application relates to digital to analogue conversion circuits having dynamic gain control. A digital variable gain element (102) may apply gain to an input digital signal (DIN) upstream of a DAC (101) to make better use of the input range of the DAC and an analogue variable gain element (103) applies a compensating analogue gain. Again controller (201) has a gain allocation module (204) for controlling the allocation of gain between said digital and analogue variable gain elements in response to changes in a signal level of the input digital audio signal. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector (202) monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection of a low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably fast enough such that the digital gain can be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.
摘要翻译：该应用涉及具有动态增益控制的数模转换电路。数字可变增益元件（102）可以对DAC（101）上游的输入数字信号（DIN）施加增益，以更好地利用DAC的输入范围，并且模拟可变增益元件（103）应用补偿模拟获得。再次，控制器（201）具有增益分配模块（204），用于响应于输入数字音频信号的信号电平的变化来控制所述数字和模拟可变增益元件之间的增益分配。在本发明中，增益分配模块可在第一和第二操作模式中操作，其中对第一模式的信号电平降低的响应比在第二操作模式中更慢。低电平检测器（202）监视输入数字音频信号，以便在检测到输入的低电平部分之后检测信号的低电平部分，并且增益控制器从第一模式改变到第二模式数字音频信号。增益分配模块在第二模式中的响应优选地足够快，使得数字增益可以在其在数字增益元件被接收之前被改变为适合于信号的低电平部分的目标设置。

10. 发明申请

US20160322984A1 COGNITIVE SIGNAL CONVERTER 有权
标题翻译：认知信号转换器
公开(公告)号：US20160322984A1
公开(公告)日：2016-11-03
申请号：US15107568
申请日：2014-12-03
申请人： Anacatum Design AB , Fingerprint Cards AB
发明人： Rolf SUNDBLAD , Staffan HOLMBRING , Robert HÄGGLUND , Emil HJALMARSSON
IPC分类号： H03M1/12 , H03M1/10 , H03M1/46 , H03M1/38
CPC分类号： H03M1/1245 , H03M1/0624 , H03M1/1009 , H03M1/1265 , H03M1/38 , H03M1/46
摘要： A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal. The cognitive network is adapted to receive the digital converted signal of the analog-to-digital converter, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.
摘要翻译：公开了一种通过模拟信号输入端口连接到模拟信号源并适于产生基于经由模拟信号输入端口接收的模拟输入信号的数字输出信号的认知信号转换器。认知信号转换器包括模数转换器和认知网络。模拟 - 数字转换器适于基于模拟输入信号，采样时钟信号和处理时钟信号，通过根据采样时钟信号对模拟输入信号进行采样并量化每个模拟输入信号来产生数字转换信号采样，其中量化处理由处理时钟信号操作。认知网络适于接收模拟 - 数字转换器的数字转换信号，基于接收的数字转换信号和模拟信号的一个或多个特性来控制采样时钟信号和处理时钟信号中的至少一个源，并且基于接收到的数字转换信号产生数字输出信号。还公开了相应的集成电路，电子设备和方法。

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