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61. 发明授权

US09281387B2 High voltage durability III-nitride device 有权
标题翻译：高耐压III族氮化物器件
公开(公告)号：US09281387B2
公开(公告)日：2016-03-08
申请号：US14459726
申请日：2014-08-14
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/778 , H01L29/04 , H01L29/20 , H01L29/66
CPC分类号： H01L29/778 , H01L21/8258 , H01L29/045 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a silicon layer, an insulator layer over the silicon layer, and a P type conductivity silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT.
摘要翻译：高耐压III族氮化物半导体器件包括：支撑衬底，其包括第一硅体，位于第一硅体上的绝缘体，以及位于绝缘体上方的第二硅体。高电压耐久性III族氮化物半导体器件还包括在第二硅体上形成的以多数电荷载流子导电型为特征的III族氮化物半导体体。第二硅体具有与多数电荷载流子导电类型相反的导电类型。在一个实施例中，高电压耐久性III族氮化物半导体器件是高电子迁移率晶体管（HEMT），其包含支撑衬底，该支撑衬底包括<100>硅层，在<100>硅层上的绝缘体层，以及P型导电性 <111>硅层。高电压耐久性HEMT还包括在P型导电性<111>硅层上形成的III族氮化物半导体体，III族氮化物半导体体形成HEMT的异质结。

62. 发明授权

US09244476B2 Electronic ballast with power factor correction 有权
标题翻译：电子镇流器，功率因数校正
公开(公告)号：US09244476B2
公开(公告)日：2016-01-26
申请号：US13715984
申请日：2012-12-14
申请人： International Rectifier Corporation
发明人： Thomas J. Ribarich , Peter Bredemeier
IPC分类号： H05B41/24 , G05F1/70 , H05B37/02 , H05B41/28 , H05B41/282 , H05B41/295
CPC分类号： G05F1/70 , H05B37/02 , H05B41/28 , H05B41/2828 , H05B41/295 , Y02B20/186
摘要： According to an exemplary implementation, an electronic ballast includes an input filter coupled to a resonant tank. The resonant tank is configured to generate a resonant current. The input filter is configured to receive an AC input voltage and to generate an AC input current from the resonant current by smoothing the resonant current. The electronic ballast also includes a half-bridge configured to feed the resonant tank so as to generate the resonant current and to receive a supply voltage that is in phase with the AC input voltage. The electronic ballast can also include a controller configured to control a power factor of the electronic ballast by switching the half-bridge. The controller can be configured to adjust a shape of the AC input current by adjusting switching of the half-bridge to thereby adjust a power factor of the electronic ballast.
摘要翻译：根据示例性实施方式，电子镇流器包括耦合到谐振槽的输入滤波器。谐振槽配置成产生谐振电流。输入滤波器被配置为接收AC输入电压并且通过平滑谐振电流从谐振电流产生AC输入电流。电子镇流器还包括配置为馈送谐振槽的半桥，以产生谐振电流并接收与AC输入电压同相的电源电压。电子镇流器还可以包括被配置为通过切换半桥来控制电子镇流器的功率因数的控制器。控制器可以被配置为通过调节半桥的切换来调节AC输入电流的形状，从而调节电子镇流器的功率因数。

63. 发明授权

US09236462B2 Programmable gate III-nitride power transistor 有权
标题翻译：可编程门III-氮化物功率晶体管
公开(公告)号：US09236462B2
公开(公告)日：2016-01-12
申请号：US13334720
申请日：2011-12-22
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/66 , H01L29/80 , H01L29/423 , H01L29/772 , H01L29/20 , H01L29/51
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.
摘要翻译：一种III族氮化物半导体器件，其包括带电的浮置栅电极。

64. 发明授权

US09219058B2 Efficient high voltage switching circuits and monolithic integration of same 有权
标题翻译：高效的高压开关电路及其整体集成
公开(公告)号：US09219058B2
公开(公告)日：2015-12-22
申请号：US13020243
申请日：2011-02-03
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/15 , H01L27/06 , H01L29/778 , H03K17/567 , H01L21/8258 , H01L29/20 , H01L27/088
CPC分类号： H01L27/0605 , H01L21/8258 , H01L27/0629 , H01L27/0883 , H01L29/2003 , H01L29/7787 , H03K17/567
摘要： A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.
摘要翻译：高压开关电路包括第一和第二组III-V晶体管，第二组III-V晶体管具有比第一组III-V晶体管更大的击穿电压。电路还包括与第一组III-V晶体管并联布置的硅二极管，并联装置与第二组III-V晶体管级联。该电路实际上是三端器件，其中第一端子耦合到第二III-V晶体管的栅极，第一III-V晶体管的源极和硅二极管的阳极。第二端子耦合到第一组III-V晶体管的栅极，并且第三端子耦合到第二组III-V晶体管的漏极。第一组III-V晶体管可以是增强型晶体管。第二组III-V晶体管可能是耗尽型晶体管。第一和第二组III-V晶体管可以是GaN HEMT。

65. 发明授权

US09202811B2 Cascode circuit integration of group III-N and group IV devices 有权
标题翻译： III-N组和IV组器件的串联电路集成
公开(公告)号：US09202811B2
公开(公告)日：2015-12-01
申请号：US14073783
申请日：2013-11-06
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L25/10 , H01L27/088 , H01L25/18 , H01L21/8258
CPC分类号： H01L27/0883 , H01L21/8258 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can be situated over the group IV transistor die.
摘要翻译：在示例性实施方案中，集成组件包括印刷电路板和耗尽型III氮化物晶体管管芯和耦合到印刷电路板的IV族晶体管管芯。耗尽型III型氮化物晶体管管芯位于印刷电路板的一侧，而IV族晶体管管芯位于印刷电路板的相对侧上。印刷电路板中的至少一个通孔将耗尽型III型氮化物晶体管管芯与第IV族晶体管管芯电连接。在一些实施方案中，耗尽型III型氮化物晶体管管芯与IV族晶体管管芯共级共栅。此外，耗尽型III型氮化物晶体管管芯可以位于IV族晶体管管芯之上。

66. 发明授权

US09196688B2 Delamination and crack prevention in III-nitride wafers 有权
标题翻译： III型氮化物晶片的分层和防裂
公开(公告)号：US09196688B2
公开(公告)日：2015-11-24
申请号：US14191910
申请日：2014-02-27
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/15 , H01L29/20 , H01L21/78
CPC分类号： H01L21/0254 , H01L21/02002 , H01L21/02373 , H01L21/02378 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/02538 , H01L21/30604 , H01L21/78 , H01L23/562 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
摘要翻译：在示例性实施方式中，一种方法包括在半导体晶片中的IV族衬底上生长III-氮化物体。该方法包括在III-氮化物体上形成至少一个器件层。该方法还包括蚀刻III-氮化物体中的栅格阵列沟槽，其中栅极阵列沟槽的蚀刻可以延伸到IV族衬底中。该方法还可以包括在半导体晶片的周边周围形成边缘沟槽。该方法还包括通过沿着栅格阵列沟槽切割半导体晶片来形成单独的管芯。

67. 发明申请

US20230113610A1 POWER SUPPLY AND EMULATED CURRENT MODE CONTROL 有权
公开(公告)号：US20230113610A1
公开(公告)日：2023-04-13
申请号：US17496804
申请日：2021-10-08
申请人： Infineon Technologies Americas Corp.
发明人： Keng Chen , James R. Garrett
IPC分类号： H02M3/158 , H02M1/36 , H02M1/08 , H02M1/084
摘要： A power supply includes a storage component to store an output current value representative of a magnitude of output current supplied by an output voltage of a power converter to power a load. The power supply further includes an offset reference generator and a controller. The offset reference generator produces an offset reference signal, the output current value being offset by the offset reference signal. The controller controls generation of the output voltage of the power converter as a function of the offset output current value with respect to a threshold signal (value). Additionally, the controller is configured to detect a startup mode of a power converter operative to convert an input voltage into an output voltage. During the startup mode, the controller: i) produces a threshold signal having a magnitude that varies over time, and ii) controls operation of switches in the power converter as a function of the threshold signal while the power converter is operated in a diode emulation mode. Implementation of the startup mode monotonically increases a magnitude of the output voltage without dips.

68. 发明申请

US20230057705A1 TRANS-INDUCTANCE MULTI-PHASE POWER CONVERTERS, MONITORING AND MANAGEMENT 有权
公开(公告)号：US20230057705A1
公开(公告)日：2023-02-23
申请号：US17409058
申请日：2021-08-23
申请人： Infineon Technologies Americas Corp.
发明人： Zhiqing YOU , Tim NG
IPC分类号： H02M3/158 , H02M1/00 , G01R31/40
摘要： An apparatus such as a power supply includes management hardware. The management hardware monitors operation of multiple power converter phases coupled in parallel to produce an output voltage. Based on the monitored operation, the management hardware determines a status of a series circuit path connecting windings of the multiple power converter phases. The management hardware produces status information indicating the status of the series circuit path.

69. 发明授权

US11535952B2 Wafer carrier and method 有权
公开(公告)号：US11535952B2
公开(公告)日：2022-12-27
申请号：US17030727
申请日：2020-09-24
申请人： Infineon Technologies Americas Corp.
发明人： Mihir Tungare , Peter Kim , Jianwei Wan , Chankyung Choi
IPC分类号： C30B25/12 , C30B25/18 , C30B29/40 , C30B29/06 , C23C16/30 , C23C16/458 , H01L21/02 , H01L21/683 , H01L21/687 , H01L23/544 , C30B25/02
摘要： A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

70. 发明授权

US11217577B2 Controlled resistance integrated snubber for power switching device 有权
公开(公告)号：US11217577B2
公开(公告)日：2022-01-04
申请号：US16789810
申请日：2020-02-13
申请人： Infineon Technologies Americas Corp.
发明人： Hugo Burke , Kapil Kelkar , Ling Ma
IPC分类号： H01L27/06 , H01L29/423 , H01L29/10 , H01L23/528 , H01L29/40 , H01L23/522 , H01L29/78 , H01L29/66 , H01L29/06 , H01L29/739
摘要： A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.

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