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61. 发明申请

US20080296173A1 Electrolysis transistor 有权
标题翻译：电解晶体管
公开(公告)号：US20080296173A1
公开(公告)日：2008-12-04
申请号：US12156178
申请日：2008-05-29
申请人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
发明人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
IPC分类号： C25B9/00 , C02F1/461
CPC分类号： C25B1/02 , C25B1/003 , C25B1/04 , C25B1/06 , C25B9/04 , C25B11/00 , C25B11/0447 , C25B15/00 , Y02E60/366 , Y02P20/135
摘要： An electrolysis transistor for providing high-density electrochemistry and products utilizing the same, and high-efficiency electrolysis and electrochemical processes is disclosed. The electrolysis transistor may comprise an electrolyte, one or more working electrodes for transferring charge to or from said electrolyte, and one or more gate structures for altering electrode over-voltage and modifying the barrier at the electrode-electrolyte interface, reducing the voltage necessary for electrolysis. An electrochemical or photo-electrochemical cell may incorporate one or more of these electrolysis transistors.
摘要翻译：公开了一种用于提供高密度电化学的电解晶体管和利用其的产品，以及高效电解和电化学方法。电解晶体管可以包括电解质，用于将电荷转移到所述电解质或从所述电解质转移电荷的一个或多个工作电极，以及用于改变电极过电压并改变电极 - 电解质界面处的阻挡层的一个或多个栅极结构，电解。电化学或光电化学电池可并入这些电解晶体管中的一种或多种。

62. 发明授权

US09935190B2 Forming enhancement mode III-nitride devices 有权
公开(公告)号：US09935190B2
公开(公告)日：2018-04-03
申请号：US15065597
申请日：2016-03-09
申请人： Transphorm Inc.
发明人： Mo Wu , Rakesh K. Lal , Ilan Ben-Yaacov , Umesh Mishra , Carl Joseph Neufeld
IPC分类号： H01L29/00 , H01L29/778 , H01L29/66 , H01L29/20 , H01L21/28 , H01L29/205 , H01L29/51 , H01L21/306 , H01L21/308 , H01L21/311 , H01L29/423 , H01L29/10 , H01L21/02
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02255 , H01L21/28264 , H01L21/30617 , H01L21/30621 , H01L21/3081 , H01L21/31144 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/4232 , H01L29/4236 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

63. 发明授权

US09865719B2 Carbon doping semiconductor devices 有权
公开(公告)号：US09865719B2
公开(公告)日：2018-01-09
申请号：US14991188
申请日：2016-01-08
申请人： Transphorm Inc.
发明人： Stacia Keller , Brian L. Swenson , Nicholas Fichtenbaum
IPC分类号： H01L29/778 , H01L21/02 , H01L29/20 , H01L29/66 , H01L29/207 , H01L29/205 , H01L29/32 , H01L29/872 , H01L29/10
CPC分类号： H01L29/7784 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/02584 , H01L21/0262 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/32 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm−3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm−2.

64. 发明授权

US09741702B2 Semiconductor power modules and devices 有权
公开(公告)号：US09741702B2
公开(公告)日：2017-08-22
申请号：US14950411
申请日：2015-11-24
申请人： Transphorm Inc.
发明人： Yifeng Wu
IPC分类号： H01L25/00 , H01L25/07 , H05K1/02 , H03K17/16 , H01L23/12 , H01L23/367 , H01L27/088 , H01L29/20 , H01L29/78 , H01L23/498 , H01L25/11 , H05K1/16 , H01L23/552 , H01L23/64 , H01L25/16
CPC分类号： H01L25/50 , H01L23/12 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L23/49844 , H01L23/552 , H01L23/642 , H01L25/074 , H01L25/117 , H01L25/16 , H01L25/165 , H01L27/0883 , H01L29/2003 , H01L29/7827 , H01L2224/48091 , H01L2924/13055 , H01L2924/30107 , H03K17/164 , H03K2217/0045 , H05K1/0218 , H05K1/0263 , H05K1/162 , H05K2201/10015 , H05K2201/10166 , H05K2201/10545 , H01L2924/00014 , H01L2924/00
摘要： An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

65. 发明授权

US09536966B2 Gate structures for III-N devices 有权
标题翻译： III-N器件的栅极结构
公开(公告)号：US09536966B2
公开(公告)日：2017-01-03
申请号：US14970375
申请日：2015-12-15
申请人： Transphorm Inc.
发明人： Tsutomu Ogino
IPC分类号： H01L29/51 , H01L29/417 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/423
CPC分类号： H01L29/41758 , H01L29/2003 , H01L29/42376 , H01L29/518 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.
摘要翻译：半导体器件包括III-N层，III-N层上的多个平行导电指状物，III-N层上的绝缘体层和栅极。多个平行导电指状物包括源极和漏极总线，多个源极连接到源极总线并且从源极总线朝向漏极总线延伸到相应的源极端部，以及多个漏极连接到漏极总线并且从漏极总线朝向源极总线延伸到相应的漏极指端，所述漏极指在所述源极指之间交叉指向。门包括多个直线和多个连接部分，每个直线部分在源极指状物和相邻的排出指状物之间，并且连接部分各自连接两个相邻的直线部分并围绕相应的源极或漏极指端部弯曲。

66. 发明授权

US09496137B2 Methods of forming reverse side engineered III-nitride devices 有权
标题翻译：形成反面工程化III族氮化物器件的方法
公开(公告)号：US09496137B2
公开(公告)日：2016-11-15
申请号：US13756284
申请日：2013-01-31
申请人： Transphorm Inc.
发明人： Rongming Chu , Umesh Mishra , Rakesh K. Lal
IPC分类号： H01L29/06 , H01L21/02 , H01L29/417 , H01L29/66 , H01L29/778 , H01L23/29 , H01L23/31 , H01L29/20 , H01L29/423 , H01L23/00
CPC分类号： H01L21/0254 , H01L23/291 , H01L23/3171 , H01L24/03 , H01L24/06 , H01L29/2003 , H01L29/4175 , H01L29/42316 , H01L29/6609 , H01L29/66462 , H01L29/7786 , H01L29/861 , H01L2224/03002 , H01L2224/03462 , H01L2224/03464 , H01L2224/04042 , H01L2224/06183 , H01L2224/94 , H01L2924/01029 , H01L2924/1032 , H01L2924/12032 , H01L2924/12042 , H01L2924/13062 , H01L2924/13064 , H01L2224/03 , H01L2924/00
摘要： Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
摘要翻译：描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。另一个钝化层位于结构的正面。在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

67. 发明授权

US09245992B2 Carbon doping semiconductor devices 有权
标题翻译：碳掺杂半导体器件
公开(公告)号：US09245992B2
公开(公告)日：2016-01-26
申请号：US14208304
申请日：2014-03-13
申请人： Transphorm Inc.
发明人： Stacia Keller , Brian L. Swenson , Nicholas Fichtenbaum
IPC分类号： H01L21/338 , H01L29/778 , H01L21/02 , H01L29/66 , H01L29/20 , H01L29/207
CPC分类号： H01L29/7784 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/02584 , H01L21/0262 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/32 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm−3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm−2.
摘要翻译：制造半导体器件的方法可以包括在反应器中形成III-N半导体层并将烃前体注入反应器，由此碳掺杂III-N半导体层并使III-N半导体层为绝缘或半绝对半导体器件可以在衬底上包括衬底和掺杂碳的绝缘或半绝缘III-N半导体层。 III-N半导体层中的碳掺杂浓度大于5×1018cm-3，III-N半导体层中的位错密度小于2×109cm-2。

68. 发明授权

US09224805B2 Semiconductor devices with guard rings 有权
标题翻译：带保护环的半导体器件
公开(公告)号：US09224805B2
公开(公告)日：2015-12-29
申请号：US14530204
申请日：2014-10-31
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Yuvaraj Dora
IPC分类号： H01L29/02 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/778 , H01L29/872 , H01L21/76 , H01L29/417 , H01L29/423 , H01L29/20
CPC分类号： H01L29/0623 , H01L21/76 , H01L29/0619 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/41766 , H01L29/42376 , H01L29/66212 , H01L29/66462 , H01L29/7786 , H01L29/872
摘要： Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.
摘要翻译：描述具有保护环的半导体器件。半导体器件可以是例如设计用于高电压应用的晶体管和二极管。保护环是由半导体材料层上方的导电材料形成的浮动电极。绝缘层的一部分位于保护环和半导体材料层的至少一部分之间。保护环可以位于例如栅极和漏极之间的晶体管上。半导体器件可以具有一个或多个保护环。

69. 发明授权

US09184275B2 Semiconductor devices with integrated hole collectors 有权
标题翻译：具有集成孔收集器的半导体器件
公开(公告)号：US09184275B2
公开(公告)日：2015-11-10
申请号：US13535094
申请日：2012-06-27
申请人： Umesh Mishra , Srabanti Chowdhury , Ilan Ben-Yaacov
发明人： Umesh Mishra , Srabanti Chowdhury , Ilan Ben-Yaacov
IPC分类号： H01L31/0328 , H01L29/778 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/20 , H01L29/207
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/7786 , H01L29/78
摘要： Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.
摘要翻译：描述了包括具有集成的空穴集电区域的半导体层的晶体管器件。空穴集电极区域被配置为在操作期间收集在晶体管器件中产生的空穴并且将它们远离器件的有源区域传送。空穴集电极区域可以电连接或耦合到器件的源极，漏极或场板。空穴集电极区域可以被掺杂，例如p型或名义上的p型，并且能够导通空穴而不是电子。

70. 发明授权

US09171910B2 Semiconductor electronic components with integrated current limiters 有权
标题翻译：具有集成限流器的半导体电子元件
公开(公告)号：US09171910B2
公开(公告)日：2015-10-27
申请号：US14311600
申请日：2014-06-23
申请人： Transphorm Inc.
发明人： Yifeng Wu , Umesh Mishra , Srabanti Chowdhury
IPC分类号： H01L27/12 , H01L29/20 , H01L29/778 , H01L27/06 , H01L27/088
CPC分类号： H01L27/0883 , H01L27/0605 , H01L29/16 , H01L29/2003 , H01L29/778 , H03K17/687
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.
摘要翻译：电子部件包括高电压耗尽型晶体管和低电压增强型晶体管。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的栅电极电耦合到低电压增强型晶体管。增强型晶体管的导通电阻小于耗尽型晶体管的导通电阻，并且增强型晶体管的最大电流电平小于耗尽型晶体管的最大电流电平。

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