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61. 发明授权

US07704787B2 Methods for fabricating phase changeable memory devices 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US07704787B2
公开(公告)日：2010-04-27
申请号：US11466302
申请日：2006-08-22
申请人： Horii Hideki , Jeong-hee Park
发明人： Horii Hideki , Jeong-hee Park
IPC分类号： H01L21/06
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that includes nitrogen atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystalline structure.
摘要翻译：提供了可变相存储器件和制造相变存储器件的方法，其包括包括氮原子的可相变材料的相变材料图案。第一和第二电极电连接到相变材料图案并向其提供电信号。相变材料图案可以具有多晶结构。

62. 发明授权

US07678606B2 Phase change memory device and fabrication method thereof 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07678606B2
公开(公告)日：2010-03-16
申请号：US11850019
申请日：2007-09-04
申请人： Frederick T Chen
发明人： Frederick T Chen
IPC分类号： H01L21/06
CPC分类号： G11C11/5678 , G11C13/0004 , H01L45/06 , H01L45/122 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer.
摘要翻译：公开了一种相变存储器件。第二导电间隔物位于第一导电间隔物下方。相变层包括基本上平行于第一和第二导电间隔物的第一部分和位于第二导电间隔物顶部上的第二部分，其中第二导电间隔物通过相变的第二部分电连接到第一导电间隔物层。

63. 发明申请

US20100055830A1 I-SHAPED PHASE CHANGE MEMORY CELL 有权
标题翻译： I型相变存储器单元
公开(公告)号：US20100055830A1
公开(公告)日：2010-03-04
申请号：US12614902
申请日：2009-11-09
申请人： Shih Hung Chen , Hsiang Lan Lung
发明人： Shih Hung Chen , Hsiang Lan Lung
IPC分类号： H01L21/06
CPC分类号： H01L27/2436 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.
摘要翻译：存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。中间绝缘层设置在与内核构件相邻的上下相变构件之间。

64. 发明授权

US07652278B2 Programmable via structure and method of fabricating same 有权
标题翻译：可编程通孔结构及其制造方法
公开(公告)号：US07652278B2
公开(公告)日：2010-01-26
申请号：US11612631
申请日：2006-12-19
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L29/02 , H01L21/06
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material.
摘要翻译：提供了可编程通孔结构以及其制造方法。本发明可编程通过半导体衬底。诸如热氧化物的氧化物层位于半导体衬底的表面上。图案化的加热材料位于氧化物层的表面上。本发明的结构还包括具有填充有相变材料（PCM）的至少一个通孔的图案化电介质材料。包括PCM填充通孔的图案化电介质材料位于图案化加热材料的表面上。图案化扩散阻挡层位于所述至少一个充满相变材料的通孔的暴露表面上。本发明的结构还包括延伸通过图案化电介质材料的接触孔。接触通孔填充有也延伸到图案化电介质材料的上表面上的导电材料。用作器件输入的导电材料位于图案化的扩散阻挡层的顶部，其位于通过相变材料填充的正上方。

65. 发明申请

US20100015757A1 BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE 有权
标题翻译：桥接电阻随机接入存储器件和具有单一接触结构的方法
公开(公告)号：US20100015757A1
公开(公告)日：2010-01-21
申请号：US12558401
申请日：2009-10-02
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/06
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.
摘要翻译：公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电极分离。电阻记忆桥与第一和第二电极的边缘表面接触。接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。位线通过自对准工艺连接到第二电极。

66. 发明申请

US20100015755A1 MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20100015755A1
公开(公告)日：2010-01-21
申请号：US12524049
申请日：2007-01-25
申请人： Yuichi Matsui , Takahiro Morikawa
发明人： Yuichi Matsui , Takahiro Morikawa
IPC分类号： H01L21/00 , H01L21/06
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： In a step of forming an InGeSbTe film which contains GeSbTe made of germanium (Ge), antimony (Sb) and tellurium (Te) as its base material and to which indium (In) is added, an InGeSbTe film is formed by sputtering on a semiconductor substrate while keeping a temperature of the semiconductor substrate between an in-situ crystallization temperature of GeSbTe serving as the base material and an in-situ crystallization temperature of InGeSbTe. As a result, it is possible to suppress the failure that the phase separation occurs in the InGeSbTe film during the following manufacturing process.
摘要翻译：在形成由锗（Ge），锑（Sb）和碲（Te）作为其基底并加入铟（In）的GeSbTe的InGeSbTe膜的步骤中，通过溅射形成InGeSbTe膜，半导体衬底，同时将半导体衬底的温度保持在用作基底材料的GeSbTe的原位结晶温度和InGeSbTe的原位结晶温度。结果，可以抑制在随后的制造过程中在InGeSbTe膜中发生相分离的故障。

67. 发明申请

US20100015753A1 High Power Efficiency, Large Substrate, Polycrystalline CdTe Thin Film Semiconductor Photovoltaic Cell Structures Grown by Molecular Beam Epitaxy at High Deposition Rate for Use in Solar Electricity Generation 有权
公开(公告)号：US20100015753A1
公开(公告)日：2010-01-21
申请号：US12505391
申请日：2009-07-17
申请人： James David Garnett
发明人： James David Garnett
IPC分类号： H01L21/06
CPC分类号： H01L31/1828 , H01L31/0296 , H01L31/02966 , H01L31/0392 , H01L31/03925 , H01L31/0725 , H01L31/073 , H01L31/078 , H01L31/1832 , H01L31/1836 , Y02E10/543 , Y02P70/521
摘要： Solar cell structures formed using molecular beam epitaxy (MBE) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using MBE are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.

68. 发明申请

US20100012915A1 PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20100012915A1
公开(公告)日：2010-01-21
申请号：US12425152
申请日：2009-04-16
申请人： Sung Min YOON , Byoung Gon YU , Soon Won JUNG , Seung Yun LEE , Young Sam PARK , Joon Suk LEE
发明人： Sung Min YOON , Byoung Gon YU , Soon Won JUNG , Seung Yun LEE , Young Sam PARK , Joon Suk LEE
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase-change memory device in which a phase-change material layer has a multilayered structure with different compositions and a method of fabricating the same are provided. The phase-change memory device includes a first electrode layer formed on a substrate, a heater electrode layer formed on the first electrode layer, an insulating layer formed on the heater electrode layer and having a pore partially exposing the heater electrode layer, a phase-change material layer formed to fill the pore and partially contacting the heater electrode layer, and a second electrode layer formed on the phase-change material layer. The main operating region functioning as a memory operating region is formed of a Ge2Sb2+xTe5 phase-change material to ensure the stability of a memory operation, and simultaneously, the subsidiary regions formed of a Ge2Sb2Te5 phase-change material are disposed respectively on and under the Ge2Sb2+xTe5 main operating region to prevent leakage of thermal energy through an electrode, thereby reducing power consumption.
摘要翻译：提供了相变材料层具有不同组成的多层结构的相变存储器件及其制造方法。相变存储器件包括形成在基板上的第一电极层，形成在第一电极层上的加热电极层，形成在加热器电极层上并具有部分地暴露加热器电极层的孔的绝缘层，形成为填充孔并且部分地接触加热器电极层的改变材料层和形成在相变材料层上的第二电极层。作为存储器工作区域的主要工作区域由Ge2Sb2 + xTe5相变材料形成，以确保存储器操作的稳定性，同时由Ge2Sb2Te5相变材料形成的辅助区域分别设置在其上 Ge2Sb2 + xTe5主要工作区域，以防止热能通过电极泄漏，从而降低功耗。

69. 发明授权

US07638357B2 Programmable resistance memory devices and systems using the same and methods of forming the same 有权
标题翻译：可编程电阻存储器件和使用该器件的系统及其形成方法
公开(公告)号：US07638357B2
公开(公告)日：2009-12-29
申请号：US11509713
申请日：2006-08-25
申请人： Jun Liu
发明人： Jun Liu
IPC分类号： H01L21/00 , H01L21/06 , H01L29/76 , H01L27/108 , H01L29/94
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/124 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed.
摘要翻译：一种可编程电阻存储元件及其形成方法。存储元件包括第一电极，位于第一电极上的电介质层和位于电介质层上的第二电极。电介质层和第二电极各自具有侧壁。一层可编程电阻材料（例如相变材料）与第一电极和电介质层和第二电极的侧壁的至少一部分接触。还公开了包括存储器元件和并入这种存储器件的系统的存储器件。

70. 发明申请

US20090291522A1 LAYOUT STRUCTURE IN SEMICONDUCTOR MEMORY DEVICE COMPRISING GLOBAL WORD LINES, LOCAL WORD LINES, GLOBAL BIT LINES AND LOCAL BIT LINES 有权
标题翻译：包含全球字线，本地字线，全球位线和本地位线的半导体存储器件中的布局结构
公开(公告)号：US20090291522A1
公开(公告)日：2009-11-26
申请号：US12509617
申请日：2009-07-27
申请人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
发明人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
IPC分类号： H01L21/06 , G11C5/02
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

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