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61. 发明授权

US5764111A Voltage controlled ring oscillator frequency multiplier 失效
标题翻译：压控环振荡器倍频器
公开(公告)号：US5764111A
公开(公告)日：1998-06-09
申请号：US801444
申请日：1997-02-18
申请人： Michael L. Bushman
发明人： Michael L. Bushman
IPC分类号： H03K3/03 , H03L7/099 , H03L7/16 , H03L7/183 , H03B27/00
CPC分类号： H03K3/0315 , H03L7/0995 , H03L7/16 , H03L2207/10 , H03L7/183
摘要： A voltage controlled ring oscillator (10) integrated with a phase locked loop (101) using CMOS technology. The ring oscillator (10) provides a frequency multiplied harmonic output frequency (42) at a frequency of 2.5 GHz or more while operating at only one-third of that frequency. The ring oscillator (10) uses an odd number of inverter stages (12, 14, 16) and provides high frequency CMOS operation by utilizing the phase shifted signals of the ring frequency at each ring inverter output (20, 24, 28). The ring oscillator (10) draws minimal current and is incorporated in a frequency synthesizer (100) used in a radio communication device (200).
摘要翻译：使用CMOS技术与锁相环（101）集成的压控环形振荡器（10）。环形振荡器（10）以2.5GHz或更高的频率提供倍频谐波输出频率（42），同时仅在该频率的三分之一处工作。环形振荡器（10）使用奇数个反相器级（12,14,16），并且通过利用每个环形反相器输出（20,24,28）处的环形频率的相移信号来提供高频CMOS操作。环形振荡器（10）吸收最小的电流，并且被并入在无线电通信装置（200）中使用的频率合成器（100）中。

62. 发明授权

US5748047A Microwave frequency generator and method of generating a desired microwave frequency signal 失效
标题翻译：微波频率发生器和产生所需微波频率信号的方法
公开(公告)号：US5748047A
公开(公告)日：1998-05-05
申请号：US689874
申请日：1996-08-15
申请人： Warren E. Guthrie , Gary S. Garbe
发明人： Warren E. Guthrie , Gary S. Garbe
IPC分类号： H03B21/02 , H03L1/02 , H03L7/00 , H03L7/16 , H04B1/26
CPC分类号： H03B21/02
摘要： A microwave frequency generator and method of generating a predetermined microwave signal. The invention comprises oscillator means to generate a determinable frequency signal and means responsive to the frequency signal received from the oscillator means to generate a predetermined Intermediate Frequency (IF) signal. The invention further includes means to generate a determinable ultrahigh frequency (UHF) signal, along with means responsive to the IF signal and to a UHF signal to generate a resultant frequency signal. Means responsive to the resultant frequency and to the predetermined frequency signal generated by the oscillator means are further provided to generate the desired predetermined microwave frequency signal.
摘要翻译：一种微波频率发生器和产生预定微波信号的方法。本发明包括产生可确定频率信号的振荡器装置和响应于从振荡器装置接收的频率信号产生预定中频（IF）信号的装置。本发明还包括用于产生可确定的超高频（UHF）信号以及响应于IF信号的装置和UHF信号以产生合成频率信号的装置。进一步提供响应于所得到的频率和由振荡器装置产生的预定频率信号的装置以产生期望的预定微波频率信号。

63. 发明授权

US5740411A Controllably switched phase locked loop circuits, systems, and methods 失效
标题翻译：可控开关锁相环电路，系统和方法
公开(公告)号：US5740411A
公开(公告)日：1998-04-14
申请号：US756669
申请日：1996-11-26
申请人： Alan S. Hearn , Larry R. Hite
发明人： Alan S. Hearn , Larry R. Hite
IPC分类号： G06F1/08 , H03L7/16 , H03L7/06
CPC分类号： G06F1/08 , H03L7/16
摘要： Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The system further includes circuitry (12c) for coupling a clock signal to the clock signal input, circuitry (28) for coupling a first clock adjustment signal to the clock adjustment signal input, and circuitry (24) for comparing the first clock adjustment signal to a second clock adjustment signal. Lastly, the system includes circuitry responsive to the comparing circuitry. This responsive circuitry includes firstly, circuitry (26) for coupling a signal to the clock signal lock input such that the phase locked loop circuit indicates an unlocked state, and secondly circuitry (22, 28) for coupling the second clock adjustment signal to the clock adjustment signal input after the phase locked loop circuit indicates an unlocked state.
摘要翻译：电路，系统和方法，涉及可控开关锁相环。该系统包括具有时钟信号输入（16c），时钟信号锁定输入（16a）和时钟调整信号输入（16b）的锁相环电路（16）。该系统还包括用于将时钟信号耦合到时钟信号输入的电路（12c），用于将第一时钟调整信号耦合到时钟调整信号输入端的电路（28）和用于将第一时钟调整信号与第二时钟调整信号。最后，系统包括响应于比较电路的电路。该响应电路首先包括用于将信号耦合到时钟信号锁定输入的电路（26），使得锁相环电路指示解锁状态，其次电路（22,28）用于将第二时钟调整信号耦合到时钟锁相环电路后的调整信号输入表示解锁状态。

64. 发明授权

US5736903A Carrier buffer having current-controlled tracking filter for spurious signal suppression 失效
标题翻译：载波缓冲器具有电流控制跟踪滤波器，用于杂散信号抑制
公开(公告)号：US5736903A
公开(公告)日：1998-04-07
申请号：US637140
申请日：1996-04-24
申请人： Brent A. Myers , Scott G. Bardsley
发明人： Brent A. Myers , Scott G. Bardsley
IPC分类号： H03L7/093 , H03L7/099 , H03L7/16
CPC分类号： H03L7/0805 , H03L7/093 , H03L7/099
摘要： Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a pre-mixer tracking filter incorporated into an emitter-coupled logic configured buffer of a carrier frequency generator, using a MOSFET-implemented current-controlled resistance component of a resistor-capacitor network and an associated current control stage. The MOSFET-implemented resistance components of the filter are controlled by the same control current that establishes the carrier generator's output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and effectively independent of process parameters.
摘要翻译：通过使用MOSFET实现的电流抑制滤波器，通过结合到载波频率发生器的发射极耦合逻辑配置缓冲器中的预混频器跟踪滤波器，实现数据通信系统的杂散能量抑制，而不使用大阶噪声抑制滤波器。电阻 - 电容网络的受控电阻分量和相关的电流控制级。滤波器的MOSFET实现的电阻分量由建立载波发生器输出频率的相同控制电流控制。因此，跟踪滤波器的截止频率与载波成线性比例，并且与工艺参数无关。

65. 发明授权

US5604468A Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same 失效
标题翻译：频率合成器具有温度补偿和倍频和提供相同的方法
公开(公告)号：US5604468A
公开(公告)日：1997-02-18
申请号：US635487
申请日：1996-04-22
申请人： Steven F. Gillig
发明人： Steven F. Gillig
IPC分类号： H03L7/18 , G06F1/08 , H03L1/02 , H03L7/00 , H03L7/08 , H03L7/183 , H03L7/185 , H03L7/197 , H03L7/06 , H03L7/16
CPC分类号： H03L7/197 , H03L1/026 , H03L7/185 , H03L7/1976 , H03L1/027
摘要： A frequency synthesizer (200) with temperature compensation and frequently multiplication. The synthesizer (200) having a temperature uncompensated frequency oscillator (202) coupled to a phase locked loop (206) including at least one temperature compensating and frequency multiplication element (208). The element (208) preferably being a multi-modulus divider. The element (208) is programmed by a control circuit (210) to vary as a function of temperature and to vary as a function of a fractional frequency multiplication factor. The element (208) also may provide adjustment of the nominal frequency of the frequency oscillator (202). The frequency oscillator (202) and preferably all the elements of the synthesizer (200) are temperature compensated by the element (208) to produce a temperature stable multiplied output frequency (238).
摘要翻译：频率合成器（200），具有温度补偿和频繁乘法。合成器（200）具有耦合到包括至少一个温度补偿和倍频元件（208）的锁相环（206）的温度未补偿的频率振荡器（202）。元件（208）优选地是多模式分配器。元件（208）由控制电路（210）编程，以作为温度的函数而变化，并且作为分数倍增因子的函数而变化。元件（208）还可以提供频率振荡器（202）的标称频率的调节。频率振荡器（202），优选地，合成器（200）的所有元件由元件（208）进行温度补偿，以产生温度稳定的乘法输出频率（238）。

66. 发明授权

US5485129A Method and apparatus for digital modulation using pulse deletion 失效
标题翻译：使用脉冲删除的数字调制方法和装置
公开(公告)号：US5485129A
公开(公告)日：1996-01-16
申请号：US376210
申请日：1995-01-20
申请人： Glen A. Franson , Peter Nanni
发明人： Glen A. Franson , Peter Nanni
IPC分类号： H03C3/09 , H04L27/12 , H03C3/00 , H03L7/16
CPC分类号： H03C3/0966 , H04L27/12
摘要： An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.
摘要翻译：一种用于产生相对于由参考信号提供的频率具有预定频移的第一和第二输出信号的装置（500）包括在一个系统中，该系统包括耦合到参考信号的锁相环（206），用于产生第一和第二输出信号。装置（500）包括耦合到参考信号的脉冲删除电路（204）和锁相环（206），用于以第一删除率从参考信号中删除脉冲，以产生第一输出信号，并用于从参考信号以产生第二输出信号。

67. 发明授权

US5481697A An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies 失效
标题翻译：一种用于以多个频率中的可选择的一个为微处理器提供时钟信号的装置，并且用于在所述多个频率中的任一个之间动态切换
公开(公告)号：US5481697A
公开(公告)日：1996-01-02
申请号：US315688
申请日：1994-09-30
申请人： Gregory Mathews , Edward Zager , Sundari Mitra
发明人： Gregory Mathews , Edward Zager , Sundari Mitra
IPC分类号： G06F1/08 , H03K5/15 , H03L7/16 , G06F1/06
CPC分类号： H03K5/15066 , G06F1/08 , H03L7/16
摘要： A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.
摘要翻译：可变频率时钟发生器以多个频率中的可选择的一个为微处理器提供互补相位时钟信号。输出可以在任何频率之间动态切换，使得相位时钟信号的每个周期的持续时间至少等于最高频率的周期持续时间。

68. 发明授权

US5402083A Shoot-through protection circuit for improved stability in a neutral-point clamped synthesizer 失效
标题翻译：直通保护电路，用于提高中性点钳位合成器的稳定性
公开(公告)号：US5402083A
公开(公告)日：1995-03-28
申请号：US73027
申请日：1993-06-07
申请人： Sampat Shekhawat , Robert C. Eckenfelder
发明人： Sampat Shekhawat , Robert C. Eckenfelder
IPC分类号： H02M1/00 , H02M1/38 , H02M7/48 , H02M7/487 , H03L7/16
CPC分类号： H02M7/487 , H02M1/38
摘要： This invention provides for an enabling circuit that ensures a positive turn-on of semiconductor switches configured for the generation of a synthesized waveform, thereby eliminating misfiring of the switches due to electronic noise or logic malfunction. The circuit is configured to separately compare a sample waveform with a positive reference voltage and a negative reference voltage. The two results are directed to separate logic AND gates which have respective control signal inputs that regulate the formation of the positive and negative portion of a synthesized waveform. The output signals from the two AND gates connect to logic means to control the firing of the semiconductor switches.
摘要翻译：本发明提供了一种使能电路，其确保配置用于产生合成波形的半导体开关的正导通，从而消除由于电子噪声或逻辑故障引起的开关的点火。该电路被配置为分别将采样波形与正参考电压和负参考电压进行比较。这两个结果针对具有调节合成波形的正和负部分的形成的各个控制信号输入的分离逻辑与门。来自两个与门的输出信号连接到逻辑装置以控制半导体开关的点火。

69. 发明授权

US5394106A Apparatus and method for synthesis of signals with programmable periods 失效
标题翻译：用于合成具有可编程周期的信号的装置和方法
公开(公告)号：US5394106A
公开(公告)日：1995-02-28
申请号：US114958
申请日：1993-08-31
申请人： Alistair D. Black , Thomas M. Tobin
发明人： Alistair D. Black , Thomas M. Tobin
IPC分类号： H03L7/16 , H03L7/18
CPC分类号： H03L7/16
摘要： A synthesized jitter generator employing a novel digital architecture is provided. The apparatus provides period synthesis and controlled sinusoidal and non-sinusoidal jitter modulation functions of a square wave provided at its output. The architecture consists of a coupling of an N+M bit digital accumulator and an N bit synchronous counter to an N bit magnitude compare circuit. The output of the magnitude compare strobes the accumulator when the two inputs are equal in magnitude causing the accumulator to increment synchronously. The output of the magnitude compare is also a digital waveform whose average period is precisely defined by the input word to the accumulator. The lower M bits of the accumulator, which are not connected to the magnitude compare and which represent fractional clock periods, are connected to a programmable delay line which provides a correction in time to the magnitude compare output so that both the instantaneous and the average periods of the digital waveform at the delay line output reflect the accumulator input word. The input to the accumulator may be varied, creating a period modulated output from the apparatus. The modulation of the digital output of the accumulator by way of an adder placed between the accumulator and the magnitude compare allows direct time (jitter) modulation of the output waveform.
摘要翻译：提供了采用新型数字架构的合成抖动发生器。该装置提供其输出端提供的方波的周期合成和受控正弦和非正弦抖动调制功能。该架构由N + M位数字累加器和N位同步计数器与N位大小比较电路的耦合组成。当两个输入的幅度相等时，幅度比较的输出选通累加器，使累加器同步增量。幅度比较的输出也是数字波形，其平均周期由输入字精确地定义到累加器。不连接到幅度比较并且表示分数时钟周期的累加器的低M位连接到可编程延迟线，该可编程延迟线在时间上提供幅度比较输出的校正，使得瞬时和平均周期的数字波形在延迟线输出反映累加器输入字。可以改变对累加器的输入，从而从设备产生周期调制的输出。通过放置在累加器和幅度比较器之间的加法器对累加器的数字输出的调制允许输出波形的直接时间（抖动）调制。

70. 发明授权

US5367212A Geometry correction waveform synthesizer 失效
标题翻译：几何校正波形合成器
公开(公告)号：US5367212A
公开(公告)日：1994-11-22
申请号：US969866
申请日：1992-10-30
申请人： Khosro M. Rabii
发明人： Khosro M. Rabii
IPC分类号： H04N3/233 , H03L7/16
CPC分类号： H04N3/2335
摘要： A geometry correction waveform synthesizer includes a plurality of DC controlled multipliers each coupled to respective sources of complimentary geometry correction signals. The DC controlled multipliers are coupled to respective gain control voltage sources as well as null adjustment voltage sources to provide a variable amplitude and polarity correction signal output. The individual correction signal outputs of the DC controlled multipliers are combined to form a composite geometry correction signal which is applied to a gain control circuit. The individual gain control signals used by the DC controlled multipliers are added to form a combined gain control signal which is used to control the composite correction signal amplitude and maintain correction signal amplitude within a predetermined range. An overall gain control couples the composite geometry correction signal to the scan system.
摘要翻译：几何校正波形合成器包括多个直流控制乘法器，每个耦合到互补几何校正信号的相应源。 DC控制的乘法器耦合到相应的增益控制电压源以及空调调节电压源，以提供可变的幅度和极性校正信号输出。 DC控制乘法器的各个校正信号输出被组合以形成应用于增益控制电路的复合几何校正信号。由DC控制的乘法器使用的各个增益控制信号相加以形成组合的增益控制信号，该组合的增益控制信号用于控制复合校正信号幅度并将校正信号幅度保持在预定范围内。整体增益控制将复合几何校正信号耦合到扫描系统。

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