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71. 发明授权

US09424190B2 Data processing system operable in single and multi-thread modes and having multiple caches and method of operation 有权
标题翻译：数据处理系统可在单线程和多线程模式下运行，并具有多个高速缓存和操作方法
公开(公告)号：US09424190B2
公开(公告)日：2016-08-23
申请号：US13213387
申请日：2011-08-19
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0813 , G06F9/30047 , G06F9/30189 , G06F9/3824 , G06F9/3851 , G06F9/3891
摘要： Systems and methods are disclosed for a computer system that includes a first load/store execution unit 210a, a first Level 1 L1 data cache unit 216a coupled to the first load/store execution unit, a second load/store execution unit 210b, and a second L1 data cache unit 216b coupled to the second load/store execution unit. Some instructions are directed to the first load/store execution unit and other instructions are directed to the second load/store execution unit when executing a single thread of instructions.
摘要翻译：公开了一种用于计算机系统的系统和方法，该计算机系统包括第一加载/存储执行单元210a，耦合到第一加载/存储执行单元的第一级1 L1数据高速缓存单元216a，第二加载/存储执行单元210b和第二L1数据高速缓存单元216b，耦合到第二加载/存储执行单元。一些指令被引导到第一加载/存储执行单元，并且当执行单个指令线程时，其他指令被引导到第二加载/存储执行单元。

72. 发明授权

US09424176B2 Robust sector ID scheme for tracking dead sectors to automate search and copydown 有权
标题翻译：用于跟踪死扇区的强大的扇区ID方案，以自动搜索和并发
公开(公告)号：US09424176B2
公开(公告)日：2016-08-23
申请号：US13776052
申请日：2013-02-25
申请人： Freescale Semiconductor, Inc.
发明人： Ross S. Scouller , Jeffrey C. Cunningham , Horacio P. Gasquet
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7209
摘要： A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.
摘要翻译：使用多个扇区状态位（451）和存储在存储器中的正向/反向跳过标志（452,453）来管理易失性存储器（20）和非易失性存储器（24）中的存储器操作，每个扇区的扇区识别记录（45），以定义顺序地布置的多个状态指示符，以指定每个存储器扇区的多个扇区配置状态，并且在正向协作期间自动绕过非易失性存储器阵列中的一个或多个死扇区和反向搜索操作。

73. 发明申请

US20160241435A1 APPARATUS FOR OPTIMISING A CONFIGURATION OF A COMMUNICATIONS NETWORK DEVICE 审中-公开
标题翻译：优化通信网络设备配置的设备
公开(公告)号：US20160241435A1
公开(公告)日：2016-08-18
申请号：US15024446
申请日：2013-09-27
申请人： Florinel IORDACHE
发明人： FLORINEL IORDACHE
IPC分类号： H04L12/24 , H04L12/26
CPC分类号： H04L41/083 , H04L41/0816 , H04L41/0823 , H04L41/20 , H04L43/026 , H04L43/04 , H04L43/062 , H04L43/0876
摘要： Apparatus (110) for configuring network equipment or devices (101a-101n) during runtime is particularly applicable to network equipment based on QorIQ (trade mark) communication platforms for DPAA (Data Path Acceleration Architecture) optimization purposes and provides a way maintaining an optimal configuration which can change over time acccording to real traffic conditions. The invention may be implemented with any kind of adaptation algorithm for targeting different DPAA features. A flow characteristic function is determined from collected traffic statistics for a multiplicity of traffic flows classified by a common property such as protocol or destination or source. Flow properties are characterised over time, past present and future prediction and in relation to other existing flows based on assigned priorities. A computed flow characteristic function represents the basis for all adaptation algorithms which may be implemented in order to optimise the various DPAA features. In contrast with conventional methods which adapt traffic to system constraints, the apparatus of the present invention itself continuously adapts to traffic dynamics in order to maintain an optimal configuration over an extended period of time.
摘要翻译：用于在运行时间期间配置网络设备（101a-101n）的设备（110）特别适用于基于用于DPAA（数据路径加速架构）优化目的的QorIQ（商标）通信平台的网络设备，并且提供了保持最佳配置的方式这可以根据实际交通状况随时间而变化。本发明可以用用于瞄准不同DPAA特征的任何种类的适配算法来实现。从通过诸如协议或目的地或源之类的公共属性分类的多个业务流的收集的流量统计来确定流特征函数。流动特性随着时间的推移，现在和将来的预测以及根据指派的优先事项与其他现有的流动有关。计算的流特征函数表示可以实现的所有适应算法的基础，以优化各种DPAA特征。与将业务调整到系统约束的传统方法相反，本发明的装置本身连续地适应业务动态，以便在延长的时间段内保持最佳配置。

74. 发明授权

US09419614B2 Low-power open-circuit detection system 有权
标题翻译：低功耗开路检测系统
公开(公告)号：US09419614B2
公开(公告)日：2016-08-16
申请号：US14843997
申请日：2015-09-03
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Yong Wang
IPC分类号： G06F21/00 , H03K19/003 , H03K5/125 , H03K3/84 , G06F21/86 , G06F21/87
CPC分类号： H03K19/003 , G06F21/86 , G06F21/87 , H01L23/576 , H03K3/84 , H03K5/125
摘要： An open-circuit detection system for an integrated circuit (IC) includes a wire (e.g., part of a wire mesh for device protection) and circuitry for detecting open-circuit conditions in the wire. A first signal generator (e.g., a linear-feedback shift register) applies a binary sequence to a first end of the wire. Switched resistors are connected between a second end of the wire and both a voltage supply and ground. A comparator compares the binary sequence and a signal based on the voltage at the second end of the wire to check for the open-circuit condition. Logic circuitry closes one of the first and second switches as a function of a value in the binary sequence. The comparator checks for the open-circuit condition in the wire randomly and intermittently, which reduces power consumption.
摘要翻译：用于集成电路（IC）的开路检测系统包括线（例如，用于器件保护的金属丝网的一部分）和用于检测线中的开路状况的电路。第一信号发生器（例如，线性反馈移位寄存器）将二进制序列应用于线的第一端。开关电阻连接在电线的第二端和电源和地之间。比较器比较二进制序列和基于电线第二端的电压的信号，以检查开路状况。逻辑电路根据二进制序列中的值来关闭第一和第二开关中的一个。比较器随机和间歇地检查电线中的开路状况，从而降低功耗。

75. 发明授权

US09419566B2 Amplifiers and related integrated circuits 有权
标题翻译：放大器及相关集成电路
公开(公告)号：US09419566B2
公开(公告)日：2016-08-16
申请号：US14009099
申请日：2011-04-20
申请人： Basim H. Noori , Gerard J. Bouisse , Jeffrey K. Jones , Jean-Christophe Nanan , Jaime A. Pla
发明人： Basim H. Noori , Gerard J. Bouisse , Jeffrey K. Jones , Jean-Christophe Nanan , Jaime A. Pla
IPC分类号： H03F1/56 , H03F3/195 , H03F3/68 , H03F1/02
CPC分类号： H03F1/565 , H01L2224/49175 , H03F1/0288 , H03F3/195 , H03F3/21 , H03F3/68 , H03F2200/222 , H03F2200/387 , H03F2200/423 , H03F2200/451
摘要： Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.
摘要翻译：提供放大器系统的装置，并提供相关的集成电路。示例性集成电路包括主放大器布置，耦合在主放大器布置的输出和集成电路的第一输出之间的第一阻抗匹配电路，峰值放大器布置和耦合在峰值放大器的输出端之间的第二阻抗匹配电路布置和集成电路的第二输出。在一个示例性实施例中，第一阻抗匹配电路和第二阻抗匹配电路具有不同的电路拓扑和不同的物理拓扑。

76. 发明授权

US09417952B2 Direct memory access (DMA) unit with error detection 有权
标题翻译：具有错误检测功能的直接存储器访问（DMA）单元
公开(公告)号：US09417952B2
公开(公告)日：2016-08-16
申请号：US14574777
申请日：2014-12-18
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Tommi M. Jokinen , Nikhil Jain , Stephen G. Kalthoff
IPC分类号： G06F11/10 , H03M13/00 , G06F13/28 , G06F13/40
CPC分类号： G06F11/1004 , G06F13/28 , G06F13/4022
摘要： Systems and methods for self-checking a direct memory access system are disclosed. These may include generating a check sum value associated with a first job of the plurality of jobs, the first job comprising a read job; if a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; generating a second check sum value associated with a last job of the plurality of jobs, the last job comprising a write job; if a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and if the second predetermined check value is not available, comparing the first check sum value with the second check sum value.
摘要翻译：公开了一种用于自我检查直接存储器存取系统的系统和方法。这些可以包括生成与多个作业中的第一作业相关联的校验和值，第一作业包括读取作业; 如果第一预定检查值可用，则将第一校验和值与第一预定校验值进行比较; 生成与所述多个作业的最后作业相关联的第二校验和值，所述最后一个作业包括写入作业; 如果第二预定检查值可用，则将第二校验和值与第二预定校验值进行比较; 并且如果第二预定检查值不可用，则将第一校验和值与第二校验和值进行比较。

77. 发明授权

US09417884B2 Method for enabling calibration during start-up of a micro controller unit and integrated circuit therefor 有权
标题翻译：用于在微控制器单元及其集成电路启动期间进行校准的方法
公开(公告)号：US09417884B2
公开(公告)日：2016-08-16
申请号：US13988425
申请日：2010-11-22
申请人： Mark Maiolani , Alistair Robertson
发明人： Mark Maiolani , Alistair Robertson
IPC分类号： G06F9/44 , F02D41/06 , F02D41/24 , F02D41/26
CPC分类号： G06F9/4401 , F02D41/064 , F02D41/2432 , F02D41/2487 , F02D41/266 , G06F9/4403
摘要： A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialization data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialization data.
摘要翻译：提供了一种用于在微控制器单元设备启动期间进行校准的方法。该方法包括在MCU设备内，从可操作地耦合到MCU设备的外部支持设备中的至少一个存储器元件读取覆盖初始化数据，以及配置MCU设备的存储器映射功能以覆盖存储在至少一部分所述MCU设备的设备存储器具有根据覆盖初始化数据存储在外部支持设备的至少一个存储器元件内的校准数据。

78. 发明授权

US09416003B2 Semiconductor die with high pressure cavity 有权
标题翻译：半导体模具采用高压腔
公开(公告)号：US09416003B2
公开(公告)日：2016-08-16
申请号：US14188649
申请日：2014-02-24
申请人： Matthieu Lagouge
发明人： Matthieu Lagouge
IPC分类号： B81B7/02 , B81C1/00 , H01L21/447
CPC分类号： B81C1/00285 , B81B2201/0235 , B81B2201/0242 , B81C2203/0118
摘要： A semiconductor die includes a device structure having a micro-electronic device located at a surface of a substrate and a cap coupled to the device structure with the micro-electronic device positioned in a cavity located between the cap and the substrate. A sacrificial material is provided within the cavity, coupling the cap to the device structure. The sacrificial material is heated in the cavity to cause the sacrificial material to decompose to a gaseous species. The presence of the gaseous species in the cavity increases a pressure level in the cavity from an initial pressure to a final pressure.
摘要翻译：半导体管芯包括具有位于衬底表面处的微电子器件的器件结构，以及耦合到器件结构的帽，微电子器件定位在位于帽和衬底之间的空腔中。在空腔内提供牺牲材料，将盖连接到装置结构。牺牲材料在空腔中被加热以使牺牲材料分解成气态物质。空腔中的气态物质的存在使空腔中的压力水平从初始压力增加到最终压力。

79. 发明授权

US09413240B2 Power converter and controller device 有权
标题翻译：电源转换器和控制器设备
公开(公告)号：US09413240B2
公开(公告)日：2016-08-09
申请号：US14540396
申请日：2014-11-13
申请人： Mohammed Mansri , Tarek Hakam , Alexandre Pujol
发明人： Mohammed Mansri , Tarek Hakam , Alexandre Pujol
IPC分类号： H02M3/158 , G05F3/08 , G06F17/50 , H02M3/156
CPC分类号： H02M3/158 , G05F3/08 , G06F17/5036 , G06F17/5072 , G06F2217/78 , H02M2003/1566
摘要： A switching power converter for DC-DC converting has an inductance coupled between a power output and a high side switch in a controller device. The controller device has an error amplifier coupled to the power output and a reference voltage for activating the high side switch. The controller device has a bypass circuit including a bypass switch coupled between the supply input and the power output, a bypass driver having a first input coupled to the power output and a second input coupled to the reference voltage, and an output coupled to the bypass switch for activating the bypass switch. The controller further has a high bypass current sensor for generating a transient signal based on a current via the bypass switch, and a bandwidth control circuit for increasing the bandwidth of the error amplifier based on the transient signal.
摘要翻译：用于DC-DC转换的开关电源转换器具有耦合在控制器装置中的功率输出和高侧开关之间的电感。控制器装置具有耦合到功率输出的误差放大器和用于激活高侧开关的参考电压。控制器装置具有旁路电路，该旁路电路包括耦合在电源输入端和电源输出端之间的旁路开关，旁路驱动器具有耦合到功率输出的第一输入和耦合到参考电压的第二输入，以及耦合到旁路的输出用于激活旁路开关的开关。控制器还具有高旁路电流传感器，用于基于经由旁路开关的电流产生瞬态信号，以及带宽控制电路，用于基于瞬态信号增加误差放大器的带宽。

80. 发明申请

US20160218830A1 PIPELINED DECODER AND METHOD FOR CONDITIONAL STORAGE 审中-公开
标题翻译：管道解码器和条件储存方法
公开(公告)号：US20160218830A1
公开(公告)日：2016-07-28
申请号：US14753136
申请日：2015-06-29
申请人： VINCENT PIERRE MARTINEZ , VOLKER DIETMAR WAHL
发明人： VINCENT PIERRE MARTINEZ , VOLKER DIETMAR WAHL
IPC分类号： H04L1/08 , H04L1/00 , G06F11/10 , H04L1/18
CPC分类号： G06F11/1004 , H04L1/0041 , H04L1/0045 , H04L1/0047 , H04L1/1812 , H04L1/1841 , H04L1/1845
摘要： A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission.The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.
摘要翻译：用于存储与传输的代码块相关联的软比特和硬比特的流水线解码器。所提出的电路在流水线解码器中减少了软比特和硬比特在接收机级所需的存储器量。也就是说，利用本申请的解决方案，当确定CRC值时，与给定代码块相关联的LLR和硬比特都可用。因此，通过本申请的流水线解码器实现所获得的非流水线解码器的效果。还公开了一种用于无线通信系统的接收机，方法和计算机程序。

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