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1. 发明授权

US11617530B2 Apparatus and methods for removing a large-signal voltage offset from a biomedical signal 有权
公开(公告)号：US11617530B2
公开(公告)日：2023-04-04
申请号：US17584076
申请日：2022-01-25
申请人： BioSig Technologies, Inc.
发明人： Budimir S. Drakulic , Sina Fakhar , Thomas G. Foxall , Branislav Vlajinic
IPC分类号： A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02 , H04L47/50 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/0215 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
摘要： Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

2. 发明授权

US11324431B2 Systems and methods for performing electrophysiology (EP) signal processing 有权
公开(公告)号：US11324431B2
公开(公告)日：2022-05-10
申请号：US16582927
申请日：2019-09-25
申请人： BioSig Technologies, Inc. , Mayo Foundation for Medical Education and Research
发明人： Budimir S. Drakulic , Sina Fakhar , Thomas G. Foxall , Branislav Vlajinic , Samuel J. Asirvatham
IPC分类号： A61B5/0215 , A61B5/30 , A61B5/00 , A61B5/0245 , A61B5/318 , A61B5/308 , H04L43/02 , H04L47/50 , G16H40/63 , A61B18/00 , H02H9/04 , H03F3/45 , H03F3/68 , H03K5/125 , A61B5/024 , A61B5/0538 , A61B18/14 , A61B5/361 , A61B5/363 , A61B5/352 , A61B5/366
摘要： Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.

3. 发明授权

US11275401B2 Tamper monitoring circuitry 有权
公开(公告)号：US11275401B2
公开(公告)日：2022-03-15
申请号：US16743585
申请日：2020-01-15
申请人： Arm Limited
发明人： Ivan Michael Lowe
IPC分类号： G06F1/10 , H03K5/125 , H03K19/20 , G01R29/02 , G08B29/08 , H03K3/037 , H03K5/00
摘要： Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

4. 发明授权

US10708191B2 Systems and methods for performing electrophysiology (EP) signal processing 有权
公开(公告)号：US10708191B2
公开(公告)日：2020-07-07
申请号：US16584167
申请日：2019-09-26
申请人： BioSig Technologies, Inc. , Mayo Foundation for Medical Education and Research
发明人： Budimir S. Drakulic , Sina Fakhar , Thomas G. Foxall , Branislav Vlajinic , Samuel J. Asirvatham
IPC分类号： A61K31/7105 , H04L12/863 , H04L12/26 , A61B5/00 , A61B5/0402 , G16H40/63 , A61B5/0428 , H03F3/45 , H03K5/125 , A61B5/0215 , A61B5/0245 , A61B5/046 , A61B5/0464 , A61B18/14 , A61B18/00 , H02H9/04 , H03F3/68 , A61B5/024 , A61B5/0456 , A61B5/0472 , A61B5/053
摘要： Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The embodiment further includes a communications interface communicatively coupled to a remote device, and a processor, coupled to the ECG circuit board, the plurality of IC circuit boards, and the communications interface. The processor is configured to receive, via the communications interface, feedback from the remote device. The processor is further configured to control, via the communication interface, the remote device based on the ECG signal, the IC signals, or the feedback from the remote device.

5. 发明授权

US09801605B2 Detection apparatus for detecting photons taking pile-up events into account 有权
公开(公告)号：US09801605B2
公开(公告)日：2017-10-31
申请号：US14362458
申请日：2012-12-13
申请人： KONINKLIJKE PHILIPS N.V.
发明人： Roland Proksa , Ewald Roessl
IPC分类号： A61B6/03 , H01L27/148 , H01L27/146 , G06F7/64 , G01T1/18 , H03K5/125 , H03K21/40 , G01R29/02 , G01R1/08 , G01R29/24 , A61B6/00 , H03K5/24 , G01R29/033 , H03K5/1252 , G01R29/027 , G01R29/08 , G01T1/17
CPC分类号： A61B6/585 , A61B6/4241 , A61B6/5205 , A61B6/5258 , A61B6/582 , A61B2560/0223 , A61B2560/0238 , G01R29/0273 , G01R29/033 , G01R29/0878 , G01R29/24 , G01T1/171 , G01T1/18 , G06F7/64 , H01L27/14856 , H03K5/1252 , H03K5/2463 , H03K21/40
摘要： The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.

6. 发明授权

US09742384B2 Comparator circuit having a calibration circuit 有权
公开(公告)号：US09742384B2
公开(公告)日：2017-08-22
申请号：US14617183
申请日：2015-02-09
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Eric Soenen , Alan Roth , Justin Shi
IPC分类号： H03K5/22 , H03K3/013 , H03K5/24 , H03K5/02 , H03K5/125
CPC分类号： H03K5/02 , H03K3/013 , H03K5/125 , H03K5/24
摘要： A comparator circuit includes a comparator, a first selection circuit, and a switched-capacitor circuit. The comparator has a first terminal, a second terminal, and an output terminal. The comparator is configured to generate an output signal at the output terminal based on a first signal on the first terminal and a second signal on the second terminal. The first selection circuit is coupled with the first terminal of the comparator and configured to selectively set a first input signal or a first calibration signal as the first signal in response to a control signal. The switched-capacitor circuit is coupled with the output terminal and the second terminal of the comparator. The switched-capacitor circuit is configured to adjust and output the second signal based on the output signal.

7. 发明授权

US09635298B2 Comparator circuit, imaging apparatus using the same, and method of controlling comparator circuit 有权
公开(公告)号：US09635298B2
公开(公告)日：2017-04-25
申请号：US14517794
申请日：2014-10-17
申请人： CANON KABUSHIKI KAISHA
发明人： Kohichi Nakamura , Hideo Kobayashi , Hiroki Hiyama , Kazuo Yamazaki
IPC分类号： H04N5/335 , H04N5/378 , H03K5/24 , H03K5/125 , H04N5/3745 , H03M1/12 , H03M1/56
CPC分类号： H04N5/378 , H03K5/125 , H03K5/249 , H03M1/1295 , H03M1/56 , H04N5/3745 , H04N5/37455
摘要： An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.

8. 发明授权

US09377526B2 Broadband frequency detector 有权
标题翻译：宽带频率检测器
公开(公告)号：US09377526B2
公开(公告)日：2016-06-28
申请号：US14758858
申请日：2014-01-07
申请人： DJP CO., LTD.
发明人： Hanyong Kim , Kyungsoo Lim
IPC分类号： H03K9/06 , G01S7/02 , H03K5/125 , G01R29/08 , G08G1/052
CPC分类号： G01S7/022 , G01R29/0871 , G01S7/021 , G01S7/023 , G01S13/0209 , G01S13/343 , G01S13/347 , G01S13/931 , G08G1/052 , H03K5/125
摘要： Provided is a broadband frequency detector, more particularly, to a frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna, wherein the second amplifier includes a transistor and a first microwave circuit unit for matching the impedance of the horn antenna and the impedance of the transistor.
摘要翻译：提供了宽带频率检测器，更具体地，涉及检测用于引导安全车辆操作的所有信号的频率检测器和用于确定车辆速度的雷达信号。宽带频率检测器包括：喇叭天线，被配置为接收具有特定频率的信号; 第一放大器，被配置为从喇叭天线接收具有特定频率的信号; 混频器单元，被配置为从第一放大器接收信号，其中信号被低噪声放大; 以及与所述放大器并联布置的第二放大器，用于在从所述喇叭天线接收的信号低噪声放大之后将信号传送到所述混频器单元，其中所述第二放大器包括晶体管和第一微波电路单元，喇叭天线和晶体管的阻抗。

9. 发明授权

US09323267B2 Method and implementation for eliminating random pulse during power up of digital signal controller 有权
标题翻译：数字信号控制器上电时消除随机脉冲的方法与实现
公开(公告)号：US09323267B2
公开(公告)日：2016-04-26
申请号：US13829972
申请日：2013-03-14
申请人： Flextronics AP, LLC
发明人： Zhen Z. Ye
IPC分类号： H02M1/00 , G05F1/67 , H03K7/08 , H03K5/125 , H02M1/36 , H02M1/42
CPC分类号： G05F1/67 , H02M1/36 , H02M1/4208 , H02M2001/0012 , H03K5/125 , H03K7/08 , Y02B70/126
摘要： A switching mode power converter includes a DSC with a digital PWM module configured for complementary operation mode during normal operation. The control algorithm of the DSC is configured such that during an initialization stage immediately following power up of the device relevant digital PWM modules used for interleaving operation are reconfigured to temporarily operate in an independent operation mode with the duty cycle associated with each channel set at zero. The reconfigured digital PWM modules remain set in the independent operation mode for a predefined period of time. Once the predefined time period is reached, the reconfigured digital PWM modules are again reconfigured back to the original complementary operation mode configuration and the control algorithm resumes normal operation of the DSC and digital PWM modules.
摘要翻译：开关模式功率转换器包括具有在正常操作期间配置为互补操作模式的数字PWM模块的DSC。 DSC的控制算法被配置为使得在用于交织操作的设备相关的数字PWM模块的紧随着上电之后的初始化阶段被重新配置为在独立操作模式下临时操作，其中每个通道设置为零的占空比。重新配置的数字PWM模块在独立操作模式下保持预定时间段。一旦达到预定义的时间段，重新配置的数字PWM模块将再次重新配置到原始的互补操作模式配置，并且控制算法恢复DSC和数字PWM模块的正常操作。

10. 发明授权

US09225320B1 High-speed clocked comparator and method thereof 有权
标题翻译：高速时钟比较器及其方法
公开(公告)号：US09225320B1
公开(公告)日：2015-12-29
申请号：US14332422
申请日：2014-07-16
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03K5/22 , H03K5/125 , H02M11/00 , H03K5/24
CPC分类号： H03K5/125 , H03K5/2481 , H03K5/249
摘要： A circuit includes a voltage-to-current converter receives a first voltage and a second voltage and outputs a first current and a second current in accordance with a clock signal. A first self-gated cascode circuit receives the first current and outputs a third current in accordance with the clock signal. A second self-gated cascode circuit receives the second current and outputs a fourth current in accordance with the clock signal. A latch circuit receives the third current and the fourth current and establishes a third voltage and a fourth voltage representing a resolution of a comparison between the third current and the fourth current, wherein the first self-gated cascode circuit is conditionally shut off based on a level of the third voltage, and the second self-gated cascode circuit is conditionally shut off based on a level of the fourth voltage.
摘要翻译：电路包括电压 - 电流转换器接收第一电压和第二电压，并且根据时钟信号输出第一电流和第二电流。第一自门式共源共栅电路接收第一电流并根据时钟信号输出第三电流。第二自门式共源共栅电路接收第二电流并根据时钟信号输出第四电流。锁存电路接收第三电流和第四电流，并建立表示第三电流和第四电流之间的比较的分辨率的第三电压和第四电压，其中第一自门式共源共栅电路基于第三电压的电平，第二自门控级联电路基于第四电压的电平有条件地切断。

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