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71. 发明授权

US08779560B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08779560B2
公开(公告)日：2014-07-15
申请号：US13964313
申请日：2013-08-12
申请人： Elpida Memory, Inc.
发明人： Seiya Fujii
IPC分类号： H01L29/40 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3135 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/18 , H01L2224/0401 , H01L2224/05082 , H01L2224/05094 , H01L2224/05096 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/11462 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/1308 , H01L2224/13082 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01037 , H01L2924/01055 , H01L2924/01084 , H01L2924/15311 , H01L2924/3011 , H01L2924/014 , H01L2224/05552
摘要： A semiconductor device includes a substrate including first and second surfaces, a first insulating film including third and fourth surfaces, the fourth surface being in contact with the first surface, and an electrode elongated to penetrate the substrate and the first insulating film, the electrode including a first portion and a second portion. The first portion includes first and second end parts and a center part sandwiched between the first and second end part. The first and second end parts of the first portion are smaller in diameter than at least a portion of the center part of the first portion. The second portion is located between the first portion and the third surface, and includes a third end part exposed from the third surface and a fourth end part connected to the first end part of the first portion.
摘要翻译：一种半导体器件，包括：包括第一和第二表面的衬底，包括第三和第四表面的第一绝缘膜，第四表面与第一表面接触;以及电极，其延伸以穿透衬底和第一绝缘膜，所述电极包括第一部分和第二部分。第一部分包括第一和第二端部以及夹在第一和第二端部之间的中心部分。第一部分的第一和第二端部的直径小于第一部分的中心部分的至少一部分。第二部分位于第一部分和第三表面之间，并且包括从第三表面露出的第三端部和连接到第一部分的第一端部的第四端部。

72. 发明授权

US09953686B2 Memory system and data transmission method 有权
公开(公告)号：US09953686B2
公开(公告)日：2018-04-24
申请号：US13764433
申请日：2013-02-11
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshinori Matsui
IPC分类号： G06F1/00 , G11C7/10 , G06F13/42 , G11C11/4093 , G11C29/02 , G11C29/50 , G11C8/18 , G11C11/401
CPC分类号： G11C7/1048 , G06F13/4243 , G06F13/4256 , G11C7/10 , G11C8/18 , G11C11/401 , G11C11/4093 , G11C29/028 , G11C29/50012
摘要： A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

73. 发明授权

US09438251B2 Clock generating circuit, semiconductor device including the same, and data processing system 有权
公开(公告)号：US09438251B2
公开(公告)日：2016-09-06
申请号：US14679450
申请日：2015-04-06
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazutaka Miyano
IPC分类号： G11C7/00 , H03L7/06 , H03L7/08 , G11C7/10 , G11C7/22 , H03L7/081 , H03L7/095 , G11C11/406
CPC分类号： H03L7/0802 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/406 , H03L7/081 , H03L7/0814 , H03L7/0816 , H03L7/095
摘要： A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.

74. 发明授权

US09431403B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431403B2
公开(公告)日：2016-08-30
申请号：US14435453
申请日：2013-10-02
申请人： PS4 Luxco S.a.r.l.
发明人： Kenji Komeda
IPC分类号： H01L27/10 , H01L27/108 , H01L49/02 , H01L21/00
CPC分类号： H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other.
摘要翻译：一种具有电容器的半导体器件，包括周期性地设置在半导体衬底上的多个圆柱形或柱状存储电极，覆盖存储电极的壁表面的电容器绝缘膜，以及设置在电容器绝缘膜上并面向电容器绝缘膜的第一导电膜存储电极，其中在其中布置有所述存储电极的第一方向上相邻的所述电容器的所述第一导电膜彼此接触，并且在剩余的存储电极布置的其它方向上相邻的电容器的第一导电膜是彼此分离。

75. 发明授权

US09418967B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09418967B2
公开(公告)日：2016-08-16
申请号：US14436028
申请日：2013-09-27
申请人： PS4 Luxco S.a.r.l.
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Dai Sasaki
IPC分类号： H01L25/065 , H01L25/18 , H01L23/31 , H01L23/50 , H01L21/56 , H01L23/32 , H01L25/07 , H01L23/48 , H01L23/522 , H01L23/528
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L23/32 , H01L23/481 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L25/065 , H01L25/07 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06596 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.
摘要翻译：半导体器件包括封装衬底，IF芯片和芯片。封装衬底具有：第一电极对准并设置在第一后表面上; 在第一前表面上沿第一方向（Y方向）排列和设置的第二电极; 以及电连接第一电极和第二电极的布线。 IF芯片具有结合到第二电极的第三电极。核心芯片连接到IF芯片。在第一方向上，IF芯片的长度大于芯片的长度，但是等于或小于封装衬底的长度。第一电极中的一个在第一方向上比芯片芯片端部更向外侧设置。所述第二电极中的至少一个在所述第一方向上比所述芯片芯片端部更向外侧配置。

76. 发明授权

US09412432B2 Semiconductor storage device and system provided with same 有权
标题翻译：半导体存储装置和系统具有相同的功能
公开(公告)号：US09412432B2
公开(公告)日：2016-08-09
申请号：US14776056
申请日：2014-03-13
申请人： PS4 Luxco S.a.r.l.
发明人： Seiji Narui , Hiromasa Noda , Chiaki Dono , Chikara Kondo , Masayuki Nakamura
IPC分类号： G11C7/00 , G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/4087 , G11C2211/4065
摘要： A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
摘要翻译：半导体存储装置具有存储单元阵列，所述存储单元阵列包括多个字线，所述多个字线包括彼此相邻的字线; 以及TRR地址转换单元，其在第一操作模式中响应于表示第一值的地址信号的输入而选择字线，并且响应于输入指示第一值的地址信号而选择字线，同时在目标行刷新模式。由于在本发明中在半导体存储装置侧执行地址转换的事实，控制装置在半导体存储装置中输出具有高访问次数的字线的地址足以在目标行刷新操作。结果，便于控制装置侧的目标行刷新操作的控制。

77. 发明授权

US09385067B2 Semiconductor device with through silicon via and alignment mark 有权
公开(公告)号：US09385067B2
公开(公告)日：2016-07-05
申请号：US14676934
申请日：2015-04-02
申请人： PS4 Luxco S.a.r.l.
发明人： Nobuyuki Nakamura
IPC分类号： H01L23/48 , H01L21/768 , H01L25/065 , H01L25/00 , H01L23/544 , H01L21/683 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号： H01L23/481 , H01L21/563 , H01L21/6836 , H01L21/76898 , H01L23/3128 , H01L23/3171 , H01L23/544 , H01L24/04 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2223/54426 , H01L2224/03002 , H01L2224/0401 , H01L2224/05572 , H01L2224/05599 , H01L2224/05647 , H01L2224/05666 , H01L2224/11005 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/13009 , H01L2224/13021 , H01L2224/13022 , H01L2224/13082 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/73204 , H01L2224/81132 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.

78. 发明授权

US09379233B2 Semiconductor device 有权
公开(公告)号：US09379233B2
公开(公告)日：2016-06-28
申请号：US14872844
申请日：2015-10-01
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshihiro Takaishi
IPC分类号： H01L29/78 , H01L29/66 , H01L27/088 , H01L21/8234
CPC分类号： H01L29/7802 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device 100 includes a plurality of vertical transistors 50 provided to stand from a silicon substrate 1 and having a pillar lower diffusion layer 9 at their end portions on the silicon substrate 1 side, a metal contact plug 31 provided to stand from the silicon substrate 1 and connected to the pillar lower diffusion layer 9 of the plurality of vertical transistors 50, the plurality of vertical transistors 50 are uniformly arranged around the metal contact plug 31 and share the pillar lower diffusion layer 9 and the metal contact plug 31.

79. 发明授权

US09379063B2 Semiconductor device and semiconductor chip 有权
公开(公告)号：US09379063B2
公开(公告)日：2016-06-28
申请号：US14803900
申请日：2015-07-20
申请人： PS4 Luxco S.a.r.l.
发明人： Keisuke Nomoto , Toru Ishikawa
IPC分类号： H01L23/48 , H01L23/538 , H01L25/065 , G11C5/02 , G11C11/4093 , G11C5/04 , H01L21/50
CPC分类号： H01L23/5384 , G11C5/02 , G11C5/04 , G11C11/4093 , G11C2207/105 , H01L21/50 , H01L23/538 , H01L25/0657 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562
摘要： The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

80. 发明授权

US09379053B2 Semiconductor device having signal line and power supply line intersecting with each other 有权
标题翻译：具有信号线和电源线的半导体装置相互交叉
公开(公告)号：US09379053B2
公开(公告)日：2016-06-28
申请号：US13786013
申请日：2013-03-05
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshimi Terui , Kazuhiko Matsuki
IPC分类号： H01L23/498 , H01L27/02 , H01L27/118 , G06F17/50
CPC分类号： H01L23/49827 , G06F17/5077 , G06F2217/02 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.
摘要翻译：本发明公开了一种半导体器件，包括：多个第一电源布线，设置在第一布线层上并沿第一方向延伸; 设置在与第一布线层不同的第二布线层上并沿与第一方向相交的第二方向延伸的多个第二电源布线; 设置在所述第二布线层上并沿所述第二方向延伸的信号线; 以及多个通孔导体，每个通孔导体将所述第一电源布线中的相关联的一个电连接到所述第二电源布线中的相关联的一个。第一电源布线的至少一部分在与信号布线相交的部分中具有凹口。

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