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1. 发明授权

US09576641B2 Semiconductor device verifying signal supplied from outside 有权
标题翻译：从外部提供的半导体器件验证信号
公开(公告)号：US09576641B2
公开(公告)日：2017-02-21
申请号：US14836315
申请日：2015-08-26
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/408 , G11C7/24 , G11C11/4076 , G11C11/4078 , G11C11/4063 , G11C11/409 , G11C8/12
CPC分类号： G11C11/409 , G11C7/24 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4078 , G11C11/408 , G11C29/52
摘要： Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
摘要翻译：这里公开了一种半导体器件，其包括基于验证结果信号和外部命令产生内部命令的访问控制电路。外部命令指示访问控制电路访问第一电路的第一命令和允许访问控制电路不访问第一电路的第二命令中的至少一个，或者允许访问控制电路保持当前状态第一个电路。访问控制电路当验证结果信号指示第一逻辑电平时，基于外部命令生成内部命令。当验证结果信号指示第二逻辑电平时，访问控制电路即使外部命令指示第一命令也生成与第二命令相对应的内部命令。

2. 发明授权

US09455019B2 Semiconductor device having CAL latency function 有权
标题翻译：具有CAL延迟功能的半导体器件
公开(公告)号：US09455019B2
公开(公告)日：2016-09-27
申请号：US14733924
申请日：2015-06-08
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/4076 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/408
CPC分类号： G11C11/4076 , G11C7/1039 , G11C7/22 , G11C8/18 , G11C11/408 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4093 , G11C11/4096
摘要： One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
摘要翻译：一个半导体器件包括接收命令信号以产生第一内部命令信号的命令接收器，以及等待时间控制电路，其在第一内部片选信号被激活之后经过时钟信号的第一周期之后激活第二内部片选信号。当时钟信号的大于第一周期的第二周期期间，当芯片选择信号保持在非活动状态时，等待时间控制电路激活第二控制信号。基于第一控制信号激活命令接收器。第一控制信号响应于第一内部芯片选择信号被激活。第一控制信号响应于第二控制信号被去激活。

3. 发明授权

US09281050B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US09281050B2
公开(公告)日：2016-03-08
申请号：US14564219
申请日：2014-12-09
申请人： PS4 LUXCO S.A.R.L.
发明人： Chikara Kondo
IPC分类号： G11C5/02 , G11C11/409 , G11C5/06 , G11C11/4063 , G11C11/4076
CPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C11/4063 , G11C11/4076 , H01L2224/16145
摘要： A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.
摘要翻译：一种用于从连接到公共命令，地址和数据总线的多个DRAM装置读取数据的方法。时钟信号被提供给多个DRAM设备。在命令和地址总线上与时钟信号同步的多个DRAM设备的读命令和地址。读取时钟信号被提供给多个DRAM设备以在由该地址选择的多个DRAM设备之一中启动读取操作。一个DRAM器件基于多个DRAM器件中的一个DRAM器件的速度来延迟读取时钟信号的量以产生。提供第一延迟读时钟和第二延迟读时钟信号。与第二延迟读时钟信号同步地在数据总线上接收读数据。

4. 发明申请

US20150364180A1 SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE 有权
标题翻译：半导体器件验证信号从外部提供
公开(公告)号：US20150364180A1
公开(公告)日：2015-12-17
申请号：US14836315
申请日：2015-08-26
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C11/408 , G11C11/409
CPC分类号： G11C11/409 , G11C7/24 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4078 , G11C11/408 , G11C29/52
摘要： Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
摘要翻译：这里公开了一种半导体器件，其包括基于验证结果信号和外部命令产生内部命令的访问控制电路。外部命令指示访问控制电路访问第一电路的第一命令和允许访问控制电路不访问第一电路的第二命令中的至少一个，或者允许访问控制电路保持当前状态第一个电路。访问控制电路当验证结果信号指示第一逻辑电平时，基于外部命令生成内部命令。当验证结果信号指示第二逻辑电平时，访问控制电路即使外部命令指示第一命令也生成与第二命令相对应的内部命令。

5. 发明授权

US09412432B2 Semiconductor storage device and system provided with same 有权
标题翻译：半导体存储装置和系统具有相同的功能
公开(公告)号：US09412432B2
公开(公告)日：2016-08-09
申请号：US14776056
申请日：2014-03-13
申请人： PS4 Luxco S.a.r.l.
发明人： Seiji Narui , Hiromasa Noda , Chiaki Dono , Chikara Kondo , Masayuki Nakamura
IPC分类号： G11C7/00 , G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/4087 , G11C2211/4065
摘要： A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
摘要翻译：半导体存储装置具有存储单元阵列，所述存储单元阵列包括多个字线，所述多个字线包括彼此相邻的字线; 以及TRR地址转换单元，其在第一操作模式中响应于表示第一值的地址信号的输入而选择字线，并且响应于输入指示第一值的地址信号而选择字线，同时在目标行刷新模式。由于在本发明中在半导体存储装置侧执行地址转换的事实，控制装置在半导体存储装置中输出具有高访问次数的字线的地址足以在目标行刷新操作。结果，便于控制装置侧的目标行刷新操作的控制。

6. 发明授权

US09225331B2 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US09225331B2
公开(公告)日：2015-12-29
申请号：US13747318
申请日：2013-01-22
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： H03K19/0175 , G11C5/02 , G11C29/12 , G11C5/04
CPC分类号： H03K19/0175 , G11C5/02 , G11C5/04 , G11C29/12 , G11C29/1201 , H01L2224/16145 , Y10T29/49004
摘要： A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M−2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M−1)-th penetration electrodes of the first semiconductor chip, respectively.
摘要翻译：一种包括第一和第二半导体芯片的装置，每个第一和第二半导体芯片包括第一至第M穿透电极，M为等于或大于3的整数，第一至第M穿透电极中的每一个穿透半导体衬底，并且第一半导体芯片包括在其输入节点处耦合到第一半导体芯片的第M个穿透电极的第一输入电路，第一和第二半导体芯片彼此堆叠，其中第一至第M 第二半导体芯片的穿透电极分别与第一半导体芯片的第一至第M穿透电极分别垂直布置，其中第二半导体芯片的第一至第（M-2）个穿透电极电耦合到分别是第一至第（M-1）个第一穿透电极。

7. 发明授权

US09053775B2 Semiconductor device having CAL latency function 有权
标题翻译：具有CAL延迟功能的半导体器件
公开(公告)号：US09053775B2
公开(公告)日：2015-06-09
申请号：US14268827
申请日：2014-05-02
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C8/18 , G11C7/10 , G11C7/22
CPC分类号： G11C11/4076 , G11C7/1039 , G11C7/22 , G11C8/18 , G11C11/408 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4093 , G11C11/4096
摘要： A method for accessing a semiconductor device having a memory array, the method includes receiving a mode register command to set a command latency value in a mode register, receiving a chip select signal, activating a command receiver in response to the chip select signal, receiving, with the command receiver, an access command with a first latency from the chip select signal equal to the command latency value, accessing the memory array in response to the access command, and deactivating the command receiver with a second latency from the chip select signal equal to a deactivation latency value.
摘要翻译：一种用于访问具有存储器阵列的半导体器件的方法，所述方法包括：接收模式寄存器命令，以在模式寄存器中设置命令延迟值，接收芯片选择信号，响应于芯片选择信号激活命令接收器，接收与命令接收器一起，具有等于命令等待时间值的芯片选择信号具有第一等待时间的访问命令，响应于访问命令访问存储器阵列，以及从芯片选择信号以第二等待时间来停止命令接收器等于停用延迟值。

8. 发明授权

US09466343B2 Semiconductor device having PDA function 有权
标题翻译：具有PDA功能的半导体器件
公开(公告)号：US09466343B2
公开(公告)日：2016-10-11
申请号：US14659757
申请日：2015-03-17
申请人： PS4 LUXCO S.A.R.L.
发明人： Chikara Kondo
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/4063 , G11C11/4093
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.
摘要翻译：一种在半导体器件中写入模式寄存器的方法，所述方法包括接收模式寄存器命令和模式信号; 产生第一模式寄存器设置信号; 延迟第一等待时间移位器中的第一模式寄存器设置信号以提供第二模式寄存器设置信号; 与第二模式寄存器设置信号同步地接收数据信号; 并且只有当所接收的数据信号具有第一逻辑电平时，才将模式信号写入模式寄存器。

9. 发明申请

US20150262648A1 SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM 有权
标题翻译：半导体器件及其调整方法及数据处理系统
公开(公告)号：US20150262648A1
公开(公告)日：2015-09-17
申请号：US14727537
申请日：2015-06-01
申请人： PS4 Luxco S.a.r.l.
发明人： Naohisa Nishioka , Chikara Kondo
IPC分类号： G11C11/4076 , G11C11/409
CPC分类号： G11C11/4076 , G06F17/5031 , G06F17/5081 , G11C5/025 , G11C7/1093 , G11C11/409 , G11C29/022 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H01L2224/16145 , H01L2924/10253 , H01L2924/1305 , H01L2924/15311 , H03L7/0814 , H01L2924/00
摘要： A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.
摘要翻译：一种方法包括将多个DRAM器件中的每一个中的输出定时调整电路复位为默认输出定时数据值，测量从读取命令到每个多个DRAM器件的数据读取的默认延迟，识别最慢的DRAM器件，从多个DRAM设备之间的读取命令到读取数据的最大默认延迟，将输出定时数据值写入多个DRAM器件中的每一个中的输出定时调整电路，以将每个相应的读取命令的延迟设置为读取数据 DRAM装置，其量基本上等于最大默认延迟，并且从读取命令延迟读取数据，以读取大致等于最大默认延迟的数据。

10. 发明授权

US09087560B2 Semiconductor device having PDA function 有权
标题翻译：具有PDA功能的半导体器件
公开(公告)号：US09087560B2
公开(公告)日：2015-07-21
申请号：US14255698
申请日：2014-04-17
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/4063
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal, generating a first mode register setting signal, delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal, receiving a data signal in synchronization with the second mode register setting signal, and writing the mode signal to the mode register only if the received data signal has a first logic level.
摘要翻译：一种用于在半导体器件中写入模式寄存器的方法，所述方法包括：接收模式寄存器命令和模式信号，产生第一模式寄存器设置信号，延迟第一等待移位器中的第一模式寄存器设置信号以提供第二模式寄存器设置信号，与第二模式寄存器设置信号同步地接收数据信号，并且仅当所接收的数据信号具有第一逻辑电平时才将模式信号写入模式寄存器。

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