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71. 发明申请

US20140085849A1 CIRCUIT BOARD SYSTEM COMPRISING A SPRING FASTENED ELEMENT 有权
标题翻译：包括弹簧紧固元件的电路板系统
公开(公告)号：US20140085849A1
公开(公告)日：2014-03-27
申请号：US14035171
申请日：2013-09-24
申请人： TELLABS OY
发明人： Antti HOLMA , Heikki JEKUNEN , Jari-Pekka LAIHONEN
IPC分类号： H05K7/12
CPC分类号： H05K7/12 , H01G2/06 , H01G9/004 , H01L2924/0002 , H01L2924/00
摘要： A circuit board system according to the invention comprises a circuit board (101), at least one element (102) mechanically supported with respect to the circuit board, and a spring-fastener (106) arranged to mechanically support the at least one element with respect to the circuit board. The spring-fastener comprises a pressing portion (107) pressing the at least one element and a latching portion (108) extending from an end of the pressing portion and being shape-locked in one or more apertures (109-110) of the circuit board. The latching portion and the one or more apertures of the circuit board are shaped to provide shape-locking whose opening requires at least a first movement of the latching portion in a first direction against the spring-force of the spring fastener and, subsequently, a second movement of the latching portion in a second direction against the spring-force of the spring fastener.
摘要翻译：根据本发明的电路板系统包括电路板（101），相对于电路板机械地支撑的至少一个元件（102）和布置成以至少一个元件机械地支撑所述至少一个元件的弹簧扣件（106）尊重电路板。弹簧扣件包括按压部分（107），该按压部分（107）压迫该至少一个元件;以及一个闩锁部分（108），其从该按压部分的一端延伸并被锁定在该电路的一个或多个孔（109-110）板。电路板的闩锁部分和一个或多个孔被成形为提供形状锁定，其开口需要克服弹簧紧固件的弹簧力而使闩锁部分在第一方向上的至少第一移动，并且随后，克服弹簧紧固件的弹簧力，使锁定部分在第二方向上的第二运动。

72. 发明申请

US20130293239A1 EQUIPMENT AND A PLUG-IN UNIT OF THE EQUIPMENT 有权
标题翻译：设备和设备的插入单元
公开(公告)号：US20130293239A1
公开(公告)日：2013-11-07
申请号：US13886451
申请日：2013-05-03
申请人： TELLABS OY
发明人： Antti HOLMA , Heikki LAAMANEN , Petri KOHONEN , Ian LEIMAN
IPC分类号： G01R31/04
CPC分类号： G01R31/041 , H05K7/1407 , H05K7/1414 , H05K7/1438
摘要： Equipment including at least one plug-in unit and a body device for receiving the plug-in unit is presented. The plug-in unit includes a mechanical structure (108) enabling the plug-in unit to be locked in its operating position with respect to the body device with a fastening element (141) that can be, for example, a fastening screw. The plug-in unit further includes a sensor circuit (111) having first electrical properties when the fastening element is in the position locking the plug-in unit in the operating position and otherwise different electrical properties. The equipment includes a monitoring circuit (112) for generating a signal indicative of a difference between the prevailing electrical properties of the sensor circuit and the first electrical properties, the signal being indicative also of correctness of the installation of the plug-in unit. Thus, the correct installation of the plug-in unit can be electrically indicated and monitored.
摘要翻译：提出了包括至少一个插件单元和用于接收插件单元的主体装置的设备。插入单元包括机械结构（108），其使得插入单元能够使用例如紧固螺钉的紧固元件（141）相对于身体装置锁定在其操作位置。插入单元还包括具有第一电气特性的传感器电路（111），当紧固元件处于将插件单元锁定在操作位置的位置和另外不同的电气特性时。该设备包括用于产生指示传感器电路的主要电气特性与第一电气特性之间的差异的信号的监视电路（112），该信号也指示插件单元安装的正确性。因此，可以电指示和监视插件单元的正确安装。

73. 发明授权

US08536960B2 Filter structure 有权
标题翻译：过滤器结构
公开(公告)号：US08536960B2
公开(公告)日：2013-09-17
申请号：US12607515
申请日：2009-10-28
申请人： Pentti Immonen , Jarno Tervo
发明人： Pentti Immonen , Jarno Tervo
IPC分类号： H01P1/203 , H01P7/08
CPC分类号： H01P1/2005 , H05K1/0236 , H05K2201/09309 , H05K2201/09681
摘要： In a filter structure for suppressing a spurious signal, a conductor layer in a printed circuit board includes a pattern with interconnected pattern elements (106 to 114). A pattern element includes a low-impedance conductive region (119) the capacitance of which against a second conductor layer of the printed circuit board is dominant over the inductance. A pattern element includes at least two adjacent high-impedance conductor strips (115, 116) in a first direction, connected to a low-impedance conductive region, and at least two adjacent high-impedance conductor strips (117, 118) in a second direction, connected to the low-impedance conductive region. The inductance of each high-impedance conductor strips is dominant over the capacitance against the second conductor layer. The high-impedance conductor strips form together with the low-impedance conductive region a plurality of resonance points in the frequency range, thus achieving sufficient stop-band width.
摘要翻译：在用于抑制寄生信号的滤波器结构中，印刷电路板中的导体层包括具有互连的图案元件（106至114）的图案。图案元件包括低电阻导电区域（119），其电容相对于印刷电路板的第二导体层占据电感的优势。图案元件包括连接到低阻抗导电区域的第一方向上的至少两个相邻的高阻抗导体条带（115,116）和连接到低阻抗导电区域的至少两个相邻的高阻抗导体条带（117,118）方向，连接到低阻抗导电区域。每个高阻抗导体条的电感优于相对于第二导体层的电容。高阻抗导体条与低阻抗导电区域一起形成频率范围内的多个谐振点，从而获得足够的阻带宽度。

74. 发明申请

US20120254677A1 METHOD AND A DEVICE FOR CONTROLLING FREQUENCY SYNCHRONIZATION 有权
标题翻译：用于控制频率同步的方法和装置
公开(公告)号：US20120254677A1
公开(公告)日：2012-10-04
申请号：US13422333
申请日：2012-03-16
申请人： Kenneth HANN , Mikko LAULAINEN
发明人： Kenneth HANN , Mikko LAULAINEN
IPC分类号： G06F11/16
CPC分类号： H04L7/033 , H03L7/08
摘要： A device for controlling frequency synchronization includes a processor (101) for controlling a phase-controlled clock signal to achieve phase-locking between the phase-controlled clock signal and a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking between the frequency-controlled clock signal and the reference clock signal. The processor is also configured to monitor a deviation between the frequency- and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal. Thus, the phase-controlled clock signal together with the information about possible changes in the circumstances is used for improving the quality of the frequency-controlled clock signal.
摘要翻译：一种用于控制频率同步的装置包括：处理器（101），用于控制相位控制的时钟信号，以实现相位控制的时钟信号和参考时钟信号之间的相位锁定，并且用于控制频率控制的时钟信号，以便实现频率控制时钟信号与参考时钟信号之间的频率锁定。处理器还被配置为监视频率和相位控制的时钟信号之间的偏差，检测诸如导致频率控制的时钟信号的频率漂移的温度变化的情况的变化，并且更换或校正频率控制的时钟信号当监视的偏差和检测到的环境变化都显示相关确认频率控制的时钟信号的频率漂移时，基于或基于相位控制的时钟信号。因此，相位控制时钟信号连同关于环境可能变化的信息被用于提高频率控制的时钟信号的质量。

75. 发明申请

US20120128369A1 TRANSCEIVER UNIT 有权
标题翻译：收发器单元
公开(公告)号：US20120128369A1
公开(公告)日：2012-05-24
申请号：US13300728
申请日：2011-11-21
申请人： Kenneth Hann
发明人： Kenneth Hann
IPC分类号： H04B10/00
CPC分类号： H03L7/07 , H04J3/047
摘要： A phase synchronized optical master-slave loop comprises at the slave-end a processor (105) configured to include a first timing signal into a bit stream to be transmitted to the master-end, detect a second timing signal from a bit stream received from the master-end, and calculate a phase difference between a regenerated phase signal and a reference phase signal on the basis of a transmission moment of the first timing signal, a first time-stamp indicating a reception moment of the first timing signal at the master-end, a reception moment of the second timing signal, and a second time-stamp indicating a transmission moment of the second timing signal from the master-end. The processor is configured to read the time stamps from the received bit stream that corresponds to a received light signal according to a reception line-code. Thus, conversion of data format is not necessary for the phase synchronization.
摘要翻译：相位同步光学主从环包括在从端处的处理器（105），被配置为将第一定时信号包括在要发送到主端的比特流中，从从第一定时信号接收的比特流中检测第二定时信号并且基于第一定时信号的传输力矩计算再生相位信号和参考相位信号之间的相位差，表示主机上的第一定时信号的接收力矩的第一时间戳 -end，第二定时信号的接收时刻，以及指示来自主端的第二定时信号的发送时刻的第二时间戳。处理器被配置为根据接收线路码从接收到的比特流读取对应于接收到的光信号的时间戳。因此，数据格式的转换对于相位同步是不必要的。

76. 发明授权

US08095711B2 Method and devices for compressing delta log using flash transactions 有权
标题翻译：使用闪存事务压缩增量日志的方法和设备
公开(公告)号：US08095711B2
公开(公告)日：2012-01-10
申请号：US12164133
申请日：2008-06-30
申请人： Matti Hallivuori
发明人： Matti Hallivuori
IPC分类号： G06F5/00
CPC分类号： H04L41/0856 , G06F11/1471 , H04L45/60 , H04L49/90
摘要： Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory.
摘要翻译：每个接收的配置数据被添加在易失性缓冲器中的下一个当前空闲位置。在添加每个接收的配置数据之后，易失性缓冲区的内容被压缩。压缩结果存储在非易失性闪存中。如果压缩结果小于限制，则允许通过下一个压缩结果在闪存中重写。如果压缩结果超过限制，则将其存储在闪存中，并将下一个压缩结果指向闪存中的不同位置。

77. 发明授权

US08081664B2 Method and arrangement for regenerating a timing signal in digital data communication 有权
标题翻译：用于在数字数据通信中再生定时信号的方法和装置
公开(公告)号：US08081664B2
公开(公告)日：2011-12-20
申请号：US11885652
申请日：2006-04-07
申请人： Mikko Laulainen
发明人： Mikko Laulainen
IPC分类号： H04J3/06 , G01R31/08 , H04B7/212 , H04L7/00
CPC分类号： H04J3/0676 , H04J3/0638
摘要： The invention relates to a method and an arrangement for regenerating a timing signal in digital data communication where two network elements operate in a master/slave loop timing mode. In a solution according to the invention two different frequency difference indicators are formed. Values or changes of the values of both of them in relation to time indicate a frequency difference between a reference timing signal present in a master device and a regenerated timing signal present in a slave device. One frequency difference indicator is formed on the basis of reception taking place in the master device, and the other one on the basis of reception taking place in the slave device. The frequency of the regenerated timing signal is adjusted utilizing information contained by both frequency difference indicators. The probability of incorrect frequency adjustment measures can be thereby reduced.
摘要翻译：本发明涉及一种在数字数据通信中再生定时信号的方法和装置，其中两个网络元件以主/从环路定时模式工作。在根据本发明的解决方案中，形成两个不同的频率差指示器。两者的值相对于时间的值或变化指示存在于主设备中的参考定时信号与从设备中存在的再生定时信号之间的频率差。基于在主设备中发生的接收而形成一个频率差指示符，另一个基于在从设备中发生的接收。利用由两个频率差指示器包含的信息来调整再生定时信号的频率。因此可以减少频率调整措施不正确的概率。

78. 发明申请

US20110258343A1 METHOD AND DEVICE FOR NETWORK ADDRESS CONFIGURATION 有权
标题翻译：网络地址配置的方法和设备
公开(公告)号：US20110258343A1
公开(公告)日：2011-10-20
申请号：US13088624
申请日：2011-04-18
申请人： Juhamatti KETTUNEN
发明人： Juhamatti KETTUNEN
IPC分类号： G06F15/16
CPC分类号： H04L29/12933 , H04L29/12283 , H04L61/2061 , H04L61/6068
摘要： A data transfer system comprises interconnected network devices organized to constitute a hierarchical logical arrangement having at least three levels of network hierarchy. A network device (102) receives from another network device (101) that is higher at the hierarchy a first data item such as an IP-prefix defining a first set of network addresses such as IP-addresses. The network device composes second data items so that each of the second data items defines one of mutually non-overlapping sub-sets of the first set. The network device transmits the second data items to network devices (104, 105) that are lower at the hierarchy in order to allocate one of the sub-sets to each of these network devices at the lower level of the hierarchy. This procedure can be repeated on all levels of the network hierarchy. Thus, the address configuration can propagate downwards through the hierarchical logical arrangement of the network devices.
摘要翻译：数据传输系统包括被组织以构成具有至少三个级别的网络层级的分级逻辑布置的互连网络设备。网络设备（102）从层级较高的另一网络设备（101）接收第一数据项，例如定义第一组网络地址（例如IP地址）的IP前缀。网络设备组成第二数据项，使得每个第二数据项定义第一组的相互不重叠的子集中的一个。网络设备将第二数据项发送到层级较低的网络设备（104,105），以便在层级的较低级别将这些子集中的一个分配给这些网络设备中的每一个。可以在网络层次结构的所有级别上重复此过程。因此，地址配置可以通过网络设备的分级逻辑布置向下传播。

79. 发明申请

US20110170445A1 METHOD AND ARRANGEMENT FOR DETERMINING TRANSMISSION DELAY DIFFERENCES 有权
标题翻译：用于确定传输延迟差异的方法和布置
公开(公告)号：US20110170445A1
公开(公告)日：2011-07-14
申请号：US13052656
申请日：2011-03-21
申请人： Sami FINÉR
发明人： Sami FINÉR
IPC分类号： H04L12/26
CPC分类号： H04L43/0852 , H04L69/28
摘要： The invention relates to determining mutual differences of transmission delays experienced by protocol data units transmitted in a communications network. This invention is based on a surprising discovery that the time difference between the receiving moments of protocol data units the temporal receiving order of which deviates from their temporal transmitting order represents the smallest possible difference between the transmission delays experienced by these protocol data units. In a method according to the invention it is determined, based on an order indicator associated with a protocol data unit received at an earlier point of time and an order indicator associated with a protocol data unit received at a later point of time, whether the mutual order of the protocol data units changed during transmission. If the mutual order has changed, the time difference between the receiving moments of the protocol data units is calculated, which time difference represents the smallest possible difference between the transmission delays experienced by these protocol data units.
摘要翻译：本发明涉及确定在通信网络中发送的协议数据单元所经历的传输延迟的相互差异。本发明基于一个惊人的发现，即时间接收顺序偏离其时间发送顺序的协议数据单元的接收时刻之间的时间差表示由这些协议数据单元经历的传输延迟之间的最小可能差异。在根据本发明的方法中，基于与在较早时间点接收的协议数据单元相关联的订单指示符和与稍后时间点接收的协议数据单元相关联的订单指示符，确定相互传输期间协议数据单元的顺序发生变化。如果相互顺序改变，则计算协议数据单元的接收时刻之间的时间差，哪个时间差表示由这些协议数据单元经历的传输延迟之间的最小可能差异。

80. 发明授权

US07969885B2 Adjusting the degree of filling of a jitter buffer 有权
标题翻译：调整抖动缓冲区的填充程度
公开(公告)号：US07969885B2
公开(公告)日：2011-06-28
申请号：US12176342
申请日：2008-07-19
申请人： Mikko Laulainen
发明人： Mikko Laulainen
IPC分类号： H04L12/26
CPC分类号： H04J3/0632 , H04J3/0664 , H04L49/90 , H04L2012/5649 , H04L2012/5681
摘要： A method and arrangement for adjusting the degree of filling of a jitter buffer in a network element receiving digital data. To the jitter buffer, there is connected a read-out unit for reading digital data from the jitter buffer. In the method, there is composed a time reserve indicator for the received protocol unit, the time reserve indicator being essentially the difference of an order indicator connected to the protocol unit and an order indicator connected to the operational cycle of the read-out unit. The time reserve indicator of the protocol unit indicates whether the protocol unit was received in good time, in order to ensure that the digital data is in the jitter buffer when the digital data is in turn to be read out. The degree of filling of a jitter buffer is adjusted on the basis of time reserve indicators composed for the received protocol units.
摘要翻译：一种用于调整接收数字数据的网络单元中的抖动缓冲器的填充程度的方法和装置。对于抖动缓冲器，连接有用于从抖动缓冲器读取数字数据的读出单元。在该方法中，构成接收到的协议单元的时间预留指示符，时间预留指示符基本上是连接到协议单元的订单指示符和连接到读出单元的操作周期的订单指示符的差。协议单元的时间保留指示符表示协议单元是否及时接收，以便在数字数据依次读出时确保数字数据位于抖动缓冲区中。基于为接收到的协议单元组成的时间预留指标，调整抖动缓冲器的填充程度。

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