专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07186569B2 Conductive memory stack with sidewall 失效
标题翻译：带侧壁的导电记忆体堆叠
公开(公告)号：US07186569B2
公开(公告)日：2007-03-06
申请号：US10605977
申请日：2003-11-11
申请人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor , Emond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor , Emond Ward
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.
摘要翻译：提供导电存储器堆叠。存储器堆叠包括底部电极，顶部电极和多电阻状态元件。多电阻状态元件被夹在电极之间，使得底部电极的顶面与多电阻状态元件的底面接触，并且顶部电极的底面与多电阻状态元件的底面接触顶面。底部电极，顶部电极和多电阻状态元件都具有与其表面相邻的侧面。此外，侧面至少部分地被侧壁层覆盖。

72. 发明申请

US20060243956A1 Cross point memory array with fast access time 有权
标题翻译：交叉点存储器阵列具有快速访问时间
公开(公告)号：US20060243956A1
公开(公告)日：2006-11-02
申请号：US11446733
申请日：2006-06-05
申请人： Darrell Rinerson , Christophe Chevallier
发明人： Darrell Rinerson , Christophe Chevallier
IPC分类号： H01L47/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.
摘要翻译：具有快速访问时间的交叉点阵列。交叉点阵列由半导体衬底上的驱动器驱动。可以定位用于单层交叉点阵列或堆叠交叉点阵列的底层的驱动程序，以改善访问时间。具体地，如果x方向驱动器位于x方向导电阵列线的中间，并且y方向驱动器位于y方向导电阵列线的中间，则存取时间将被改善。

73. 发明授权

US07099179B2 Conductive memory array having page mode and burst mode write capability 有权
标题翻译：具有页面模式和突发模式写入能力的导电存储器阵列
公开(公告)号：US07099179B2
公开(公告)日：2006-08-29
申请号：US10745178
申请日：2003-12-22
申请人： Darrell Rinerson , Christophe Chevallier
发明人： Darrell Rinerson , Christophe Chevallier
IPC分类号： G11C11/00 , G11C7/10 , G11C7/02 , G11C7/00 , G11C8/00
CPC分类号： G11C13/0007 , G11C7/1015 , G11C7/1018 , G11C8/12 , G11C11/16 , G11C11/5685 , G11C13/0069 , G11C2013/0085 , G11C2013/009 , G11C2213/31 , G11C2213/34 , G11C2213/77 , G11C2213/79 , H01L27/101
摘要： Conductive memory array having page mode and burst mode write capability. The conductive memory array includes two-terminal memory plugs and driver circuits configured to write information to the memory plugs in two cycles. The array also includes associated circuitry that allows it to carry out such two-cycle writes in either page mode or burst mode.
摘要翻译：具有页面模式和突发模式写入能力的导电存储器阵列。导电存储器阵列包括两端存储器插头和被配置为在两个周期内将信息写入存储器插头的驱动器电路。该阵列还包括相关电路，允许其以页模式或突发模式执行这种两周期写入。

74. 发明授权

US07095644B2 Conductive memory array having page mode and burst mode read capability 有权
标题翻译：具有页面模式和突发模式读取能力的导电存储器阵列
公开(公告)号：US07095644B2
公开(公告)日：2006-08-22
申请号：US10745264
申请日：2003-12-22
申请人： Christophe Chevallier , Darrell Rinerson
发明人： Christophe Chevallier , Darrell Rinerson
IPC分类号： G11C11/00
CPC分类号： G11C7/1027 , G11C7/1021 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , G11C2213/79 , H01L27/101
摘要： Conductive memory array having page mode and burst mode read capability. The conductive memory array includes two-terminal memory plugs and sensing circuits configured to read information from the memory plugs in two cycles. The array also includes associated circuitry that allows it to carry out such two-cycle reads in either page mode or burst mode.
摘要翻译：具有页面模式和突发模式读取能力的导电存储器阵列。导电存储器阵列包括两端存储器插头和被配置为以两个周期从存储器插头读取信息的感测电路。阵列还包括相关电路，允许它以页模式或突发模式执行这样的两周期读取。

75. 发明授权

US07057914B2 Cross point memory array with fast access time 失效
公开(公告)号：US07057914B2
公开(公告)日：2006-06-06
申请号：US10612776
申请日：2003-07-01
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

76. 发明授权

US07042035B2 Memory array with high temperature wiring 失效
标题翻译：内存阵列采用高温接线
公开(公告)号：US07042035B2
公开(公告)日：2006-05-09
申请号：US10765406
申请日：2004-01-26
申请人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/2436 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/77 , H01L27/2418 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines and barrier layers. Such structures are then exposed to the high temperature processing steps and should be resistant to such temperatures.
摘要翻译：提供了具有可承受高温制造的部件的存储器阵列。一些记忆材料需要高温工艺步骤才能达到所需的性能。在制造期间，将记忆材料沉积在可以包括金属线和阻挡层的结构上。然后将这种结构暴露于高温加工步骤，并且应该能够抵抗这种温度。

77. 发明申请

US20060083055A1 Providing a reference voltage to a cross point memory array 有权
标题翻译：向交叉点存储器阵列提供参考电压
公开(公告)号：US20060083055A1
公开(公告)日：2006-04-20
申请号：US11288472
申请日：2005-11-28
申请人： Darrell Rinerson , Christophe Chevallier
发明人： Darrell Rinerson , Christophe Chevallier
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C5/147 , G11C11/15 , G11C13/0004 , G11C2213/31
摘要： Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.
摘要翻译：向交叉点存储器阵列提供参考电压。本发明是一种交叉点存储器阵列和一些外围电路，当被激活时，该交叉点存储器阵列向交叉点阵列提供参考电压。外围电路可在特定内存插头选择之前，之后或期间激活。如果外围电路在选择期间被激活，则只有未选择的导电阵列线才能被带到参考电压。否则，所有导电阵列线可以被带到参考电压。

78. 发明授权

US06992922B2 Cross point memory array exhibiting a characteristic hysteresis 有权
标题翻译：具有特征滞后的交叉点存储器阵列
公开(公告)号：US06992922B2
公开(公告)日：2006-01-31
申请号：US11047952
申请日：2005-01-31
申请人： Darrell Rinerson
发明人： Darrell Rinerson
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.
摘要翻译：提供具有表现出特征滞后的存储插件的交叉点存储器阵列。存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，低于该电压脉冲将改变电阻内存插头。类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

79. 发明授权

US06965137B2 Multi-layer conductive memory device 有权
标题翻译：多层导电存储器件
公开(公告)号：US06965137B2
公开(公告)日：2005-11-15
申请号：US10605757
申请日：2003-10-23
申请人： Wayne Kinney , Steven W. Longcor , Darrell Rinerson , Steve Kuo-Ren Hsia
发明人： Wayne Kinney , Steven W. Longcor , Darrell Rinerson , Steve Kuo-Ren Hsia
IPC分类号： G11C11/56 , G11C13/00 , H01L27/24 , H01L31/062
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2418 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by intentionally doping the conductive metal oxide layers that are comprised of substantially similar materials. Methods of manufacture are also provided herein.
摘要翻译：提供能够单独存储信息或作为存储器件阵列的一部分的多层导电存储器件。通过有意地掺杂由基本相似的材料构成的导电金属氧化物层，可以避免由于使用不相容的材料而在器件层之间的界面处的边界控制问题。本文还提供了制造方法。

80. 发明授权

US06909632B2 Multiple modes of operation in a cross point array 有权
标题翻译：交叉点阵列中的多种操作模式
公开(公告)号：US06909632B2
公开(公告)日：2005-06-21
申请号：US10921037
申请日：2004-08-17
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Edmond R. Ward , Wayne Kinney , Steve Kuo-Ren Hsia
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Edmond R. Ward , Wayne Kinney , Steve Kuo-Ren Hsia
IPC分类号： G11C11/56 , G11C13/00 , G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.
摘要翻译：交叉点阵列中的多种操作模式。本发明是在读取模式期间使用导电阵列线对上的读取电压的交叉点阵列。当读取电流处于第一电平并且当读取电流处于第二电平时，读取电压产生指示第一编程状态的读取电流，并且指示第二编程状态。读取电流无效，导致程序状态的变化。如果希望从第二编程状态改变到第一编程状态，则在第一写入模式期间使用第一电压脉冲。如果希望从第一编程状态改变到第二编程状态，则在第二写入模式期间使用第二电压脉冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式