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71. 发明授权

US09231139B2 Structure and design of concentrator solar cell assembly receiver substrate 有权
标题翻译：集中器太阳能电池组件接收器基板的结构与设计
公开(公告)号：US09231139B2
公开(公告)日：2016-01-05
申请号：US13249686
申请日：2011-09-30
申请人： Michael A. Gaynes , Yves C. Martin , Jay E. Pogemiller , Aparna Prabhakar , Theodore G. van Kessel , Brent A. Wacaser
发明人： Michael A. Gaynes , Yves C. Martin , Jay E. Pogemiller , Aparna Prabhakar , Theodore G. van Kessel , Brent A. Wacaser
IPC分类号： H01L31/0232 , H01L31/052 , H01L31/02 , H01L31/054
CPC分类号： H01L31/052 , H01L31/02008 , H01L31/0521 , H01L31/0543 , Y02E10/52
摘要： A substrate has a top side and a bottom side. A solar cell is secured to the top side of the substrate and has an anode and a cathode. A heat transfer element is secured to the bottom side of the substrate. An anode pad is formed on the top side of the substrate and is coupled to the anode of the solar cell; similarly, a cathode pad is formed on the top side of the substrate and is coupled to the cathode of the solar cell. The substrate coefficient of thermal expansion and the solar cell coefficient of thermal expansion match within plus or minus ten parts per million per degree C.
摘要翻译：基板具有顶侧和底侧。太阳能电池固定到基板的顶侧，并具有阳极和阴极。传热元件固定到基底的底侧。阳极焊盘形成在衬底的顶侧，并且耦合到太阳能电池的阳极; 类似地，阴极焊盘形成在衬底的顶侧上并耦合到太阳能电池的阴极。基板的热膨胀系数和太阳能电池的热膨胀系数在每摄氏度百万分之内加上十度以内。

72. 发明授权

US09152223B2 Mobile device with multiple security domains 有权
标题翻译：具有多个安全域的移动设备
公开(公告)号：US09152223B2
公开(公告)日：2015-10-06
申请号：US13667130
申请日：2012-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David L. Cohn , Guerney D. H. Hunt , James Randal Moulic , Dimitrios Pendarakis
IPC分类号： G06F15/173 , G06F3/01 , G06F11/20 , G06F9/46 , G06F15/78 , H04W12/08
CPC分类号： G06F21/53 , G06F3/01 , G06F3/0484 , G06F9/468 , G06F11/20 , G06F11/2005 , G06F11/201 , G06F11/2033 , G06F11/2089 , G06F15/173 , G06F15/7871 , G06F2221/034 , H04W12/08
摘要： Included within a shared housing are at least one user interface element; a first isolated computational entity; a second isolated computational entity; and a switching arrangement. The switching arrangement is configured to, in a first mode, connect the first isolated computational entity to the at least one user interface element; and, in a second mode, connect the second isolated computational entity to the at least one user interface element.
摘要翻译：包含在共享外壳内的是至少一个用户界面元素; 第一个隔离的计算实体; 第二个隔离计算实体; 和切换装置。切换装置被配置为在第一模式中将第一隔离计算实体连接到至少一个用户接口元件; 并且在第二模式中，将所述第二隔离计算实体连接到所述至少一个用户界面元素。

73. 发明授权

US09147615B2 Ambipolar synaptic devices 有权
标题翻译：双极突触装置
公开(公告)号：US09147615B2
公开(公告)日：2015-09-29
申请号：US14181245
申请日：2014-02-14
申请人： International Business Machines Corporation
发明人： Ali Afzali-Ardakani , Tze-Chiang Chen , Kailash Gopalakrishnan , Bahman Hekmatshoartabari
IPC分类号： H01L21/20 , H01L21/8238 , H01L29/778 , H01L29/66 , H01L29/267 , H01L29/08 , H01L29/165
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
摘要翻译：基于捕获和去除捕获空穴或电子和/或两种载体的复合的装置结构通过在接近界面深双极态或量子阱/点中的载流子捕获来获得，其用作半导体层中的双极阱，或者在栅介质/阻挡层中。在任一情况下，捕获的势垒很小，并且通过在深陷阱状态和/或量子阱/点中的载流子限制提供保留。设备架构可用作三个终端或两个终端设备。

74. 发明授权

US09110777B2 Reducing performance degradation in backup semiconductor chips 有权
标题翻译：降低备份半导体芯片的性能下降
公开(公告)号：US09110777B2
公开(公告)日：2015-08-18
申请号：US13396345
申请日：2012-02-14
申请人： Aditya Bansal , Manjul Bhushan , Keith A. Jenkins , Jae-Joon Kim , Barry P. Linder , Kai Zhao
发明人： Aditya Bansal , Manjul Bhushan , Keith A. Jenkins , Jae-Joon Kim , Barry P. Linder , Kai Zhao
IPC分类号： G06F1/26 , G06F11/00 , H04M15/00 , G06F1/20 , G06F1/32 , G06F17/50 , G06F11/20
CPC分类号： G06F11/004 , G06F1/206 , G06F1/3293 , G06F11/00 , G06F11/2041 , G06F11/2043 , G06F17/505 , G06F2217/70 , G06F2217/72 , G06F2217/80 , H04M15/00 , Y02D10/122 , Y02D10/16
摘要： A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.
摘要翻译：系统具有至少第一电路部分和第二电路部分。第一电路部分以正常交流频率工作。第二电路部分以低AC频率在备用模式下操作，使得第二电路部分可以快速上线，但是温度偏差不稳定性降低有限。然后可以将第二电路部分在线并在正常交流频率下操作。还提供了包括第一和第二电路部分和控制单元以及计算机程序产品的系统。

75. 发明授权

US09103972B2 Optical waveguide structure with waveguide coupler to facilitate off-chip coupling 有权
标题翻译：具有波导耦合器的光波导结构，有利于片外耦合
公开(公告)号：US09103972B2
公开(公告)日：2015-08-11
申请号：US14019518
申请日：2013-09-05
申请人： International Business Machines Corporation
发明人： Russell A. Budd , Fuad E. Doany , Christopher V. Jahnes , Benjamin G. Lee , Laurent Schares
IPC分类号： G02B6/12 , G02B6/136
CPC分类号： G02B6/26 , G02B6/12 , G02B6/12002 , G02B6/12004 , G02B6/132 , G02B6/136 , G02B6/2821 , G02B6/305
摘要： Aspects of the invention are directed to a method for forming an optical waveguide structure. Initially, a base film stack is received with an optical waveguide feature covered by a lower dielectric layer. An etch stop feature is then formed on the lower dielectric layer, and an upper dielectric layer is formed over the etch stop feature. Subsequently, a trench is patterned in the upper dielectric layer and the etch stop feature at least in part by utilizing the etch stop feature as an etch stop. Lastly, a waveguide coupler feature is formed in the trench, at least a portion of the waveguide coupler feature having a refractive index higher than the lower dielectric layer and the upper dielectric layer. The waveguide coupler feature is positioned over at least a portion of the optical waveguide feature but is separated from the optical waveguide feature by a portion of the lower dielectric layer.
摘要翻译：本发明的方面涉及一种用于形成光波导结构的方法。首先，接收具有被下介电层覆盖的光波导特征的基膜叠层。然后在下介电层上形成蚀刻停止特征，并且在蚀刻停止特征上形成上介电层。随后，至少部分地通过利用蚀刻停止特征作为蚀刻停止，在上电介质层和蚀刻停止特征中图案化沟槽。最后，波导耦合器特征形成在沟槽中，波导耦合器特征的至少一部分具有高于下介电层和上电介质层的折射率。波导耦合器特征位于光波导特征的至少一部分上，但是通过下介电层的一部分与光波导特征分离。

76. 发明授权

US09093533B2 FinFET structures having silicon germanium and silicon channels 有权
标题翻译：具有硅锗和硅通道的FinFET结构
公开(公告)号：US09093533B2
公开(公告)日：2015-07-28
申请号：US13950173
申请日：2013-07-24
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L29/06 , H01L21/8234 , H01L29/66 , H01L21/02 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/02381 , H01L21/02532 , H01L21/033 , H01L21/2018 , H01L21/2053 , H01L21/3065 , H01L21/308 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/16 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7855
摘要： Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.
摘要翻译：在半导体晶片或其它基板上形成硅和硅锗翅片，以便于产生紧密间隔的nFET和pFET器件。在形成填充凹部的硅锗层的外延生长之前，使用图案化心轴层在晶片中形成一个或多个凹槽。间隔件形成在图案化心轴层的侧壁上，随后移除心轴层。蚀刻在间隔物之间的晶片和硅锗层的暴露区域以形成可用于来自晶片的nFET器件的鳍片和可用于来自硅锗层的pFET器件的鳍片。

77. 发明授权

US09064743B2 Flexible, stretchable electronic devices 有权
标题翻译：灵活，可伸缩的电子设备
公开(公告)号：US09064743B2
公开(公告)日：2015-06-23
申请号：US14556200
申请日：2014-11-30
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Wilfried E. Haensch , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/01 , H01L27/12 , H01L23/14 , H01L27/092
CPC分类号： H01L23/14 , H01L21/4846 , H01L21/7624 , H01L23/5381 , H01L23/5386 , H01L23/5387 , H01L27/092 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.
摘要翻译：公开了制造方法，其有助于电子结构的制造，所述电子结构既柔软又可拉伸，以符合非平面（例如弯曲）表面，而不会由于过度应变而遭受功能损伤。提供包括CMOS器件的电子结构，其可以在可接受的范围内被拉伸或挤压而不会发生故障或断裂。本文公开的方法进一步有助于生产具有多级片内连接器的柔性，可拉伸的电子结构。这种连接器通过沉积和光刻图案（线处理的后端）形成，并且可以在将电子结构转移到柔性基板之后被释放。

78. 发明授权

US09058209B2 Methods and apparatus for efficient tone detection 有权
标题翻译：用于高效音调检测的方法和装置
公开(公告)号：US09058209B2
公开(公告)日：2015-06-16
申请号：US13442169
申请日：2012-04-09
申请人： Gil Naveh
发明人： Gil Naveh
IPC分类号： G06F17/10 , G06F7/50 , G06F7/52
CPC分类号： G06F7/50 , G06F7/52 , G06F17/10 , H04M7/129 , H04M7/1295 , H04Q1/4575
摘要： An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.
摘要翻译：用于确定输入信号中存在音调的装置包括耦合到存储器电路的存储器电路和数据处理电路。数据处理电路可操作以接收输入信号的多个样本，并且至少部分地通过将每个样本乘以用于脉冲响应的第一组值的相应值并将结果相加来确定第一值。所述数据处理系统还可操作以至少部分地通过将所述样本的每一个乘以脉冲响应的第二组值并将结果相加来确定第二值。数据处理系统至少部分地通过利用第一值和第二值来确定输入信号的多个样本中的音调的功率。

79. 发明授权

US09036430B2 FinFET-based boosting supply voltage circuit and method 有权
公开(公告)号：US09036430B2
公开(公告)日：2015-05-19
申请号：US13951585
申请日：2013-07-26
申请人： International Business Machines Corporation
发明人： Rajiv V. Joshi , Keunwoo Kim
IPC分类号： G11C7/00 , G11C11/419 , G11C5/14
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C11/417
摘要： A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

80. 发明授权

US09015783B2 Bandwidth conservation 有权
标题翻译：带宽保护
公开(公告)号：US09015783B2
公开(公告)日：2015-04-21
申请号：US12718371
申请日：2010-03-05
申请人： Matthew C. Smith
发明人： Matthew C. Smith
IPC分类号： H04N7/173 , H04N21/462 , H04N21/2662
CPC分类号： H04N7/173 , H04N21/2385 , H04N21/2393 , H04N21/25435 , H04N21/25825 , H04N21/25866 , H04N21/2662 , H04N21/4621 , H04N21/47202 , H04N21/658
摘要： A request to establish a switched digital video session with high-definition content is received from a subscriber of a video content network offering a switched digital video service. A determination is made that the subscriber only has capability of viewing standard definition content. Responsive to the request and the determination, the subscriber, in the session, is provided a signal with a standard definition version of the requested high-definition content. An exemplary switched digital video control apparatus and an exemplary system are also disclosed.
摘要翻译：从提供切换数字视频服务的视频内容网络的用户接收到建立具有高清内容的交换数字视频会话的请求。确定订户仅具有查看标准清晰度内容的能力。响应于请求和确定，会话中的用户被提供具有所请求的高清内容的标准清晰度版本的信号。还公开了示例性的交换数字视频控制装置和示例性系统。

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