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71. 发明授权

US07530094B2 Method and apparatus for facilitating single sign-on of an application cluster 有权
标题翻译：用于促进应用集群单点登录的方法和装置
公开(公告)号：US07530094B2
公开(公告)日：2009-05-05
申请号：US10405434
申请日：2003-04-01
申请人： Andrew B. Philips , Marilyn Joyce Schneider Hollinger
发明人： Andrew B. Philips , Marilyn Joyce Schneider Hollinger
IPC分类号： G06F7/04 , G06F17/30 , G06K9/00 , H04L9/32
CPC分类号： H04L63/0815 , G06F21/41 , H04L63/083
摘要： One embodiment of the present invention provides a system that facilitates single sign-on of an application cluster, wherein the application cluster includes a plurality of computer applications residing on the same computer system. The system operates by first receiving a logon request at a server from the application cluster, wherein the logon request specifies an account for the server. Next, the system authenticates the application cluster to the server and determines if the application cluster is authorized to use the specified account. If so, the system authorizes the application cluster to use the specified account.
摘要翻译：本发明的一个实施例提供一种促进应用集群的单一登录的系统，其中应用集群包括驻留在同一计算机系统上的多个计算机应用。系统通过首先从应用程序集群在服务器处接收登录请求来操作，其中登录请求指定服务器的帐户。接下来，系统将应用集群认证到服务器，并确定应用集群是否被授权使用指定的帐户。如果是这样，系统授权应用程序集群使用指定的帐户。

72. 发明授权

US07529911B1 Hardware-based technique for improving the effectiveness of prefetching during scout mode 有权
标题翻译：基于硬件的技术，用于提高侦察模式下预取的有效性
公开(公告)号：US07529911B1
公开(公告)日：2009-05-05
申请号：US11139866
申请日：2005-05-26
申请人： Lawrence A. Spracklen , Yuan C. Chou , Santosh G. Abraham
发明人： Lawrence A. Spracklen , Yuan C. Chou , Santosh G. Abraham
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3861
摘要： One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in scout mode, wherein instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. When the system executes a load instruction during scout mode, if the load instruction causes a lower-level cache miss, the system allows the load instruction to access a higher-level cache. Next, the system places the load instruction and subsequent dependent instructions into a deferred queue, and resumes execution of the program in scout mode. If the load instruction ultimately causes a hit in the higher-level cache, the system replays the load instruction and subsequent dependent instructions in the deferred queue, whereby the value retrieved from the higher-level cache can help in generating prefetches during scout mode.
摘要翻译：本发明的一个实施例提供一种提高在侦察模式下执行指令期间预取的有效性的系统。在遇到非数据相关失速条件时，系统执行检查点并开始执行侦察模式中的指令，其中推测性地执行指令以预取未来的存储器操作，但是其中结果未被提交到处理器的架构状态。当系统在侦察模式下执行加载指令时，如果加载指令导致较低级别的高速缓存未命中，则系统允许加载指令访问更高级别的缓存。接下来，系统将加载指令和后续相关指令放入延迟队列中，并以侦察模式恢复执行程序。如果加载指令最终导致高级缓存中的命中，则系统在延迟队列中重放加载指令和后续相关指令，由此从较高级别缓存中检索的值可以帮助在侦察模式下产生预取。

73. 发明授权

US07526482B2 System and method for enabling components on arbitrary networks to communicate 有权
标题翻译：用于使任意网络上的组件通信的系统和方法
公开(公告)号：US07526482B2
公开(公告)日：2009-04-28
申请号：US10212377
申请日：2002-08-01
申请人： Warren Keith Edwards , Mark Webster Newman , Trevor Smith , Jana Zdislava Sedivy , Karen Marcelo , Shahram Izadi , Jason Hong
发明人： Warren Keith Edwards , Mark Webster Newman , Trevor Smith , Jana Zdislava Sedivy , Karen Marcelo , Shahram Izadi , Jason Hong
IPC分类号： G06F17/30 , G06F15/173 , H04W4/00
CPC分类号： G06F9/54 , G06F17/30067 , H04L29/06 , H04L67/10 , H04L67/16 , H04L67/34 , H04L69/08 , H04L69/329
摘要： A system for enabling components on arbitrary networks to communicate includes a plurality of arbitrary components, such as computers, servers, laptops, facsimile machines, copier machines and cellular telephones, including applications operating on those components, such as word processing or data base applications, connected together by one or more networks that may use the same or different protocols. A method includes a first component, such as a computer, obtaining aggregate objects from other components, such as a laptop or server. Each of the aggregate objects are associated with discovered component objects of the other components, such as the laptop or server. The first component selects at least one of the components associated with the aggregate objects, and invokes universal interfaces associated with the selected arbitrary components to communicate with other arbitrary components.
摘要翻译：用于使得任意网络上的组件能够通信的系统包括多个任意组件，诸如计算机，服务器，膝上型计算机，传真机，复印机和蜂窝电话，包括在诸如文字处理或数据库应用之类的那些组件上操作的应用程序，由可能使用相同或不同协议的一个或多个网络连接在一起。一种方法包括诸如计算机的第一组件，从诸如膝上型计算机或服务器的其他组件获得聚合对象。每个聚合对象与其他组件（例如笔记本电脑或服务器）的已发现组件对象相关联。第一个组件选择与聚合对象相关联的至少一个组件，并且调用与所选任意组件相关联的通用接口以与其他任意组件通信。

74. 发明授权

US07523344B2 Method and apparatus for facilitating process migration 有权
标题翻译：促进过程迁移的方法和装置
公开(公告)号：US07523344B2
公开(公告)日：2009-04-21
申请号：US11471351
申请日：2006-06-19
申请人： Donghai Qiao , Sanjeev M. Bagewadi , Pramod Batni
发明人： Donghai Qiao , Sanjeev M. Bagewadi , Pramod Batni
IPC分类号： G06F11/00
CPC分类号： G06F11/2046 , G06F11/203
摘要： A system that migrates a process from a source computer system to a target computer system. During operation, the system generates a checkpoint for the process on the source computer system, wherein the checkpoint includes a kernel state for the process. Next, the system swaps out dirty pages of a user context for the process to a storage device which is accessible by both the source computer system and the target computer system and transfers the checkpoint to the target computer system. The system then loads the kernel state contained in the checkpoint into a skeleton process on the target computer system. Next, the system swaps in portions of the user context for the process from the storage device to the target computer system and resumes execution of the process on the target computer system.
摘要翻译：将进程从源计算机系统迁移到目标计算机系统的系统。在操作期间，系统为源计算机系统上的进程生成检查点，其中检查点包括进程的内核状态。接下来，系统将进程的用户上下文的脏页面交换到可由源计算机系统和目标计算机系统访问的存储设备，并将检查点传送到目标计算机系统。然后，系统将包含在检查点中的内核状态加载到目标计算机系统上的骨架进程中。接下来，系统将用于进程的用户上下文的一部分从存储设备切换到目标计算机系统，并且在目标计算机系统上恢复该过程的执行。

75. 发明授权

US07523266B2 Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level 有权
标题翻译：在L1高速缓存级别执行存储器引用排序要求的方法和装置
公开(公告)号：US07523266B2
公开(公告)日：2009-04-21
申请号：US11592836
申请日：2006-11-03
申请人： Shailender Chaudhry , Marc Tremblay
发明人： Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30189 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.
摘要翻译：本发明的一个实施例提供了一种在多处理器中的级别1（L1）高速缓存上实施存储器参考排序要求（诸如总存储订购（TSO））的系统。在操作期间，当以推测执行模式执行指令时，系统在L1高速缓存中接收用于高速缓存线的无效信号，其中从多处理器内的高速缓存相干系统接收到无效信号。响应于无效信号，如果高速缓存行存在于L1高速缓存中，则系统检查高速缓存行中的加载标记，其中设置的加载标记指示在推测执行期间已经加载了高速缓存行。如果设置了加载标记，则系统将失败推测执行模式，并从检查点恢复正常执行模式。通过失败推测执行模式，系统确保由无效信号指示的高速缓存行的潜在更新不会导致在推测执行模式期间违反存储器引用排序要求。

76. 发明授权

US07518881B2 Interposer containing bypass capacitors for reducing voltage noise in an IC device 失效
标题翻译：包含用于降低IC器件电压噪声的旁路电容器的插入器
公开(公告)号：US07518881B2
公开(公告)日：2009-04-14
申请号：US11781116
申请日：2007-07-20
申请人： William P. Cornelius
发明人： William P. Cornelius
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H01L24/10 , H01L23/49822 , H01L23/50 , H01L24/13 , H01L24/73 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/19106 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.
摘要翻译：本发明的一个实施例提供一种降低集成电路（IC）装置的电压噪声的装置。该装置包括被配置为夹在IC器件和电路板之间的插入器。该插入器具有底表面，其被配置为接收来自电路板的电源，接地和其它信号的电连接，以及顶表面，其被配置为向IC设备提供用于电力，接地和其它信号的电连接。多个旁路电容器被集成到插入器中并且耦合在用于IC器件的电源和接地连接之间，使得多个旁路电容器降低用于IC器件的电源和接地连接之间的电压噪声。

77. 发明授权

US07500086B2 Start transactional execution (STE) instruction to support transactional program execution 有权
标题翻译：启动事务执行（STE）指令以支持事务性程序执行
公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： G06F9/40 , G06F15/00
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译：本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。

78. 发明授权

US07496880B2 Method and apparatus for assessing the quality of a process model 有权
标题翻译：评估过程模型质量的方法和装置
公开(公告)号：US07496880B2
公开(公告)日：2009-02-24
申请号：US11243306
申请日：2005-10-03
申请人： Lawrence S. Melvin, III , Qiliang Yan
发明人： Lawrence S. Melvin, III , Qiliang Yan
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： One embodiment of the present invention provides a system that assesses the quality of a process model. During operation, the system receives a mask layout and additionally receives a process model that models the effects of one or more semiconductor manufacturing processes on the mask layout. Next, the system computes a gradient of the process model with respect to a process model parameter. The system then computes a quality indicator at an evaluation point in the mask layout using the gradient of the process model and the mask layout. Next, the system assesses the quality of the process model using the quality indicator. In one embodiment, the system assesses the quality of the process model by comparing the quality indicator with a threshold.
摘要翻译：本发明的一个实施例提供了一种评估过程模型的质量的系统。在操作期间，系统接收掩模布局，并且另外接收对掩模布局中的一个或多个半导体制造工艺的影响进行建模的过程模型。接下来，系统计算相对于过程模型参数的过程模型的梯度。然后，系统使用过程模型和掩模布局的梯度在掩模布局中的评估点处计算质量指标。接下来，系统使用质量指标来评估过程模型的质量。在一个实施例中，系统通过将质量指标与阈值进行比较来评估过程模型的质量。

79. 发明授权

US07487149B2 Method and apparatus for providing query-level security in a database system 有权
标题翻译：在数据库系统中提供查询级安全性的方法和装置
公开(公告)号：US07487149B2
公开(公告)日：2009-02-03
申请号：US10800315
申请日：2004-03-10
申请人： Daniel ManHung Wong
发明人： Daniel ManHung Wong
IPC分类号： G06F17/30
CPC分类号： G06F21/6227 , G06F17/30979 , Y10S707/99933 , Y10S707/99936
摘要： One embodiment of the present invention provides a system that facilitates using query signatures to provide security for a database system. During operation, the database system receives a query. Next, the system parses the query to determine a signature for the query. This signature specifies a structure based on operators for the query and is independent of the value of literals in the query. The system then determines if the signature can be found in a signature cache which contains valid query signatures. If so, the system processes the query.
摘要翻译：本发明的一个实施例提供一种便于使用查询签名为数据库系统提供安全性的系统。在操作期间，数据库系统接收到查询。接下来，系统解析查询以确定查询的签名。该签名指定了基于查询的运算符的结构，并且与查询中文字的值无关。然后，系统确定签名是否可以在包含有效查询签名的签名高速缓存中找到。如果是这样，系统处理查询。

80. 发明授权

US07475047B1 Parallel grouping decomposition for fast training of large-scale support vector machines 有权
标题翻译：用于大规模支持向量机的快速训练的并行分组分解
公开(公告)号：US07475047B1
公开(公告)日：2009-01-06
申请号：US11081983
申请日：2005-03-16
申请人： Aleksey M. Urmanov , Anton A. Bougaev , Kenny C. Gross
发明人： Aleksey M. Urmanov , Anton A. Bougaev , Kenny C. Gross
IPC分类号： G06F15/18
CPC分类号： G06K9/6269 , G06N99/005 , Y10S706/924
摘要： One embodiment of the present invention provides a system that performs parallel grouping decomposition to facilitate expedited training of a support vector machine (SVM). During operation, the system receives a training dataset comprised of data vectors. The system then determines whether any data vector in the dataset violates conditions associated with a current SVM. Next, the system divides the violating data vectors into a number of subsets, thereby allowing parallel SVM training for each subset. The system subsequently builds an independent SVM for each subset in parallel based on the current SVM. The system then constructs a new SVM to replace the current SVM based on the SVMs built for each subset of violating data vectors.
摘要翻译：本发明的一个实施例提供一种执行并行分组分解以促进支持向量机（SVM）的加速训练的系统。在操作期间，系统接收由数据向量组成的训练数据集。然后，系统确定数据集中的任何数据向量是否违反与当前SVM相关联的条件。接下来，系统将违规数据向量划分成多个子集，从而允许每个子集的并行SVM训练。该系统随后基于当前SVM并行构建每个子集的独立SVM。然后，该系统构建新的SVM，以基于针对违规数据向量的每个子集构建的SVM来替换当前SVM。

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