专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08745419B2 Logical power throttling of instruction decode rate for successive time periods 有权
标题翻译：连续时间段的逻辑功率节制指令解码速率
公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

2. 发明授权

US08732407B2 Deadlock avoidance during store-mark acquisition 有权
标题翻译：存储标记采集期间的死锁避免
公开(公告)号：US08732407B2
公开(公告)日：2014-05-20
申请号：US12273697
申请日：2008-11-19
申请人： Robert E. Cypher , Haakan E. Zeffer , Shailender Chaudhry
发明人： Robert E. Cypher , Haakan E. Zeffer , Shailender Chaudhry
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译：本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他线程尝试存储标记相同的缓存行。

3. 发明授权

US08601240B2 Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution 有权
标题翻译：在推测执行期间遇到具有未知目的地地址的存储指令后，选择性地推迟加载指令
公开(公告)号：US08601240B2
公开(公告)日：2013-12-03
申请号：US12773661
申请日：2010-05-04
申请人： Shailender Chaudhry , Martin R. Karlsson , Gideon N. Levinsky
发明人： Shailender Chaudhry , Martin R. Karlsson , Gideon N. Levinsky
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3832 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3863
摘要： The described embodiments provide a system for executing instructions in a processor. While executing instructions in an execute-ahead mode, the processor encounters a store instruction for which a destination address is unknown. The processor then defers the store instruction. Upon encountering a load instruction while the store instruction with the unknown destination address is deferred, the processor determines if the load instruction is to continue executing. If not, the processor defers the load instruction. Otherwise, the processor continues executing the load instruction.
摘要翻译：所描述的实施例提供了一种用于在处理器中执行指令的系统。当以执行方式执行指令时，处理器遇到目标地址未知的存储指令。然后，处理器延迟存储指令。当具有未知目的地地址的存储指令被延迟时遇到加载指令，处理器确定加载指令是否继续执行。如果没有，则处理器延迟加载指令。否则，处理器继续执行加载指令。

4. 发明授权

US08484434B2 Index generation for cache memories 有权
标题翻译：高速缓存存储器的索引生成
公开(公告)号：US08484434B2
公开(公告)日：2013-07-09
申请号：US13402796
申请日：2012-02-22
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F13/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

5. 发明申请

US20110264862A1 REDUCING PIPELINE RESTART PENALTY 有权
标题翻译：减少管道重启罚款
公开(公告)号：US20110264862A1
公开(公告)日：2011-10-27
申请号：US12768641
申请日：2010-04-27
申请人： Martin Karlsson , Sherman H. Yip , Shailender Chaudhry
发明人： Martin Karlsson , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F12/0855
摘要： Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.
摘要翻译：公开了关于减少在实现侦察的处理器中重新启动管道的延迟的技术。在一个实施例中，处理器可以使用配置为彼此并行地获取和重新获取指令的两个指令获取单元来减少流水线重新启动等待时间。在一些实施例中，响应于确定将针对一个或多个延迟指令尝试提交操作，处理器可以通过启动重新获取指令来减少流水线重新启动等待时间。在其他实施例中，处理器可以通过响应于接收到对高速缓存已经接收到对一组数据的请求的指示，通过发起重新获取指令来减少流水线重新启动等待时间，其中在由缓存发送指示之前，数据存在于缓存中。

6. 发明申请

US20100268919A1 METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM 有权
标题翻译：解决双向问题的方法与结构
公开(公告)号：US20100268919A1
公开(公告)日：2010-10-21
申请号：US12426550
申请日：2009-04-20
申请人： Shailender Chaudhry , Marc Tremblay
发明人： Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30112 , G06F9/30138 , G06F9/3838 , G06F9/384
摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
摘要翻译：在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。状态信息保存在每个n位寄存器的寄存器文件中。通过连续名称空间检测指令对其他指令的依赖性。状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

7. 发明授权

US07730265B1 Starvation-avoiding unbounded transactional memory 有权
标题翻译：饥饿 - 避免无限交易记忆
公开(公告)号：US07730265B1
公开(公告)日：2010-06-01
申请号：US11715243
申请日：2007-03-06
申请人： Robert E. Cypher , Shailender Chaudhry
发明人： Robert E. Cypher , Shailender Chaudhry
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.
摘要翻译：本发明的一个实施例提供一种促进有效的事务执行的系统。在操作期间，系统执行针对线程的避免饥饿事务，其中执行避免饥饿事务涉及：（1）在避免饥饿交易期间加载的高速缓存线上放置加载标记; （2）将存储标记放置在在饥饿 - 避免交易期间存储的高速缓存行上; 和（3）将时间戳值写入用于加载标记和存储标记的高速缓存行的元数据。当线程正在执行避免饥饿事务时，系统会阻止其他线程执行另一个避免饥饿事务。由于加载标记和存储标记防止在饥饿 - 避免事务处理期间来自其他线程的访问到缓存线。

8. 发明申请

US20100125707A1 DEADLOCK AVOIDANCE DURING STORE-MARK ACQUISITION 有权
标题翻译：在商店收购期间的死亡避险
公开(公告)号：US20100125707A1
公开(公告)日：2010-05-20
申请号：US12273697
申请日：2008-11-19
申请人： Robert E. Cypher , Haakan E. Zeffer , Shailender Chaudhry
发明人： Robert E. Cypher , Haakan E. Zeffer , Shailender Chaudhry
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
摘要翻译：本发明的一些实施例提供了一种在尝试在高速缓存行上获取存储标记时避免死锁的系统。在操作期间，系统跟踪在执行线程期间出现的存储标记请求，其中高速缓存行上的存储标记指示一个或多个关联的存储缓冲器条目正在等待被提交到高速缓存行。在该系统中，存储标记请求以流水线方式处理，这允许在对同一线程完成的先前存储标记请求之前启动存储标记请求。接下来，如果存储标记请求失败，则在有限的时间内，系统会删除或防止与同一线程的较小的存储标记请求相关联的存储标记，从而避免当一个或多个其他线程尝试存储标记相同的缓存行。

9. 发明申请

US20100031084A1 CHECKPOINTING IN A PROCESSOR THAT SUPPORTS SIMULTANEOUS SPECULATIVE THREADING 审中-公开
标题翻译：在支持同时进行线性加工的处理器中进行检查
公开(公告)号：US20100031084A1
公开(公告)日：2010-02-04
申请号：US12185683
申请日：2008-08-04
申请人： Marc Tremblay , Shailender Chaudhry
发明人： Marc Tremblay , Shailender Chaudhry
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G06F9/30043 , G06F9/3005 , G06F9/30127 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Embodiments of the present invention provide a system for executing program code on a processor. In these embodiments, the processor is configured to start by using a primary strand to execute program code. Upon detecting a predetermined condition, the processor is configured to instantaneously checkpoint an architectural state of the primary strand and then use the subordinate strand to copy the checkpointed state to memory while using the primary strand to continue executing the program code without interruption.
摘要翻译：本发明的实施例提供一种用于在处理器上执行程序代码的系统。在这些实施例中，处理器被配置为通过使用主链来执行程序代码。在检测到预定条件时，处理器被配置为立即检查主链的架构状态，然后使用下级链将检查点状态复制到存储器，同时使用主链继续执行程序代码而不中断。

10. 发明申请

US20100023701A1 CACHE LINE DUPLICATION IN RESPONSE TO A WAY PREDICTION CONFLICT 有权
标题翻译：响应方式预测冲突的缓存行重复
公开(公告)号：US20100023701A1
公开(公告)日：2010-01-28
申请号：US12181266
申请日：2008-07-28
申请人： Shailender Chaudhry , Robert E. Cypher , Martin Karlsson
发明人： Shailender Chaudhry , Robert E. Cypher , Martin Karlsson
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a corresponding entry in the way prediction table. The system then checks for the presence of the cache line in the predicted way. Upon determining that the cache line is not present in the predicted way, but is present in a different way, and hence the way was mispredicted, the system increments a corresponding record in a conflict detection table. Upon detecting that a record in the conflict detection table indicates that a number of mispredictions equals a predetermined value, the system copies the corresponding cache line from the way where the cache line actually resides into the predicted way.
摘要翻译：本发明的实施例提供了一种在多路缓存中处理方式错误预测的系统。系统通过接收访问多路缓存中的高速缓存行的请求来启动。对于每个请求，系统基于方式预测表中的相应条目来预测高速缓存行驻留的方式。然后，系统以预测的方式检查高速缓存行的存在。在确定高速缓存行不以预测的方式存在但是以不同的方式存在，并且因此错误地预测方式时，系统在冲突检测表中增加对应的记录。当检测到冲突检测表中的记录指示许多误预测值等于预定值时，系统将高速缓存行实际驻留的方式的相应高速缓存行复制到预测的方式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式