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71. 发明申请

US20140179068A1 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH LOW CURRENT STRUCTURES AND METHODS THEREOF 有权
标题翻译：具有低电流结构的读/写元件的三维阵列的非易失性存储器及其方法
公开(公告)号：US20140179068A1
公开(公告)日：2014-06-26
申请号：US14149601
申请日：2014-01-07
申请人： SanDisk 3D LLC
发明人： George Samachisa , Johann Alsmeier
IPC分类号： H01L21/306 , H01L21/762
CPC分类号： H01L27/11551 , G11C5/025 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/306 , H01L21/76224 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/1226 , H01L45/1273 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
摘要翻译：在位于半导体衬底上方不同距离的多个平面层上形成三维阵列读/写（R / W）存储元件。优选以低电流和高电阻状态操作R / W元件。这些电阻状态的电阻也取决于R / W元件的尺寸，并且由工艺技术预先确定。与R / W元件串联的片状电极及其形成方法提供了另一个自由度来调节R / W存储元件的电阻。调整片状电极的厚度，以便在从字线到位线的电路中获得减小的截面接触。这允许R / W存储元件具有大大增加的电阻，因此以大大减小的电流工作。片状电极形成的电池尺寸几乎没有增加。

72. 发明申请

US20140177315A1 Multi-Level Memory Array Having Resistive Elements For Multi-Bit Data Storage 有权
标题翻译：具有用于多位数据存储的电阻元件的多级存储器阵列
公开(公告)号：US20140177315A1
公开(公告)日：2014-06-26
申请号：US13721279
申请日：2012-12-20
申请人： Intermolecular Inc. , SanDisk 3D LLC , Kabushiki Kaisha Toshiba
发明人： Dipankar Pramanik , David E. Lazovsky , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/145 , H01L45/1608
摘要： A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
摘要翻译：提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

73. 发明申请

US20140175364A1 RADIATION ENHANCED RESISTIVE SWITCHING LAYERS 有权
标题翻译：辐射增强电阻开关层
公开(公告)号：US20140175364A1
公开(公告)日：2014-06-26
申请号：US13722155
申请日：2012-12-20
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2463 , H01L45/08 , H01L45/146 , H01L45/1641
摘要： Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.
摘要翻译：提供了辐射增强的电阻式开关层，包括这些层的电阻随机存取存储器（ReRAM）单元，以及形成这些层和单元的方法。辐射在电阻开关材料中产生缺陷，允许在这些材料中形成和断开导电路径，从而提高其电阻开关特性。例如，电离辐射可以破坏用于这种层的各种材料中的化学键，而非电离辐射可以形成电子陷阱。可以控制辐射功率，打盹等处理特性，以产生电阻式开关层内的缺陷分布。例如，通过层的厚度的缺陷的不均匀分布可能有助于降低开关电压和/或电流。可以在热退火之前或之后进行辐射，其可以用于控制电阻开关层中辐射产生的缺陷和其他类型的缺陷的分布。

74. 发明申请

US20140175360A1 Bilayered Oxide Structures for ReRAM Cells 审中-公开
标题翻译：用于ReRAM电池的双层氧化物结构
公开(公告)号：US20140175360A1
公开(公告)日：2014-06-26
申请号：US13721358
申请日：2012-12-20
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Mihir Tendulkar , Vidyut Gopal , Imran Hashim , Randall J. Higuchi , Tim Minvielle , Yun Wang , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2481 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1625
摘要： Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells.
摘要翻译：提供了具有双层金属氧化物结构的电阻随机存取存储器（ReRAM）单元。双层结构的层可以具有不同的组成和厚度。具体地说，一层可以比另一层薄一些，有时可以减薄5至20倍。较薄的层可以小于30埃厚或甚至小于10埃厚。较薄的层通常比较厚的层富氧。较薄层的缺氧可能小于5原子％或甚至小于2原子％。在一些实施方案中，可以使用最高氧化态金属氧化物来形成较薄的层。较薄的层通常直接与一个电极（例如由掺杂多晶硅制成的电极）接合。将这些特定配置的层组合成双层结构允许改善ReRAM单元的成形和操作特性。

75. 发明申请

US20140175356A1 Resistive Random Access Memory Access Cells Having Thermally Isolating Structures 有权
标题翻译：具有热隔离结构的电阻随机存取存储器存取单元
公开(公告)号：US20140175356A1
公开(公告)日：2014-06-26
申请号：US13721658
申请日：2012-12-20
申请人： INTERMOLECULAR INC. , KABUSHIKI KAISHA TOSHIBA , SANDISK 3D LLC
发明人： Yun Wang , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1293 , H01L27/2481 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.
摘要翻译：提供了电阻随机存取存储器（ReRAM）单元，其包括电阻开关层和用于在操作期间限制来自开关层的散热的热隔离结构。热隔离结构可以位于堆叠内或邻近堆叠。例如，堆叠可以包括一个或两个热隔离结构。热隔离结构可以直接与开关层接口或者可以通过例如电极分离。热分离结构可以由导热率小于1W / m×K的材料形成，例如多孔二氧化硅和中孔氧化钛。与开关层串联设置的隔热结构通常具有小于开关层的低电阻状态的电阻。位于与开关层相邻的隔热结构可具有大于开关层的高电阻状态的电阻。

76. 发明授权

US08742392B2 Bipolar multistate nonvolatile memory 有权
标题翻译：双极多态非易失性存储器
公开(公告)号：US08742392B2
公开(公告)日：2014-06-03
申请号：US13953296
申请日：2013-07-29
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Tony Chiang
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616
摘要： Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含通过使用多层可变电阻层而具有改进的器件开关容量的电阻式开关存储器元件。在一个实施例中，电阻式开关元件包括至少三层可变电阻材料以增加逻辑状态的数量。每个可变电阻层可以具有相关联的高电阻状态和相关联的低电阻状态。由于每个可变电阻层的电阻决定了存储的数字数据位，每个存储元件的多个可变电阻层允许额外的数据存储，而不需要进一步增加非易失性存储器件的密度。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

77. 发明授权

US08741768B2 Method for reducing dielectric overetch when making contact to conductive features 有权
标题翻译：在与导电特征接触时减小介质过蚀刻的方法
公开(公告)号：US08741768B2
公开(公告)日：2014-06-03
申请号：US13938975
申请日：2013-07-10
申请人： SanDisk 3D LLC
发明人： Christopher J. Petti
IPC分类号： H01L21/311
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
摘要翻译：提供了一种方法，其包括在第一电介质材料之上形成导电或半导体特征，在导电或半导体特征之上沉积第二电介质材料，蚀刻第二电介质材料中的空隙，其中蚀刻停止在第一电介质材料上，导电或半导体特征的一部分。提供了许多其他方面。

78. 发明申请

US20140134794A1 Nonvolatile Memory Device Having An Electrode Interface Coupling Region 审中-公开
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US20140134794A1
公开(公告)日：2014-05-15
申请号：US14156762
申请日：2014-01-16
申请人： Intermolecular Inc. , SanDisk 3D LLC , Kabushiki Kaisha Toshiba
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

79. 发明申请

US20140119858A1 Semiconductor Device Manufacturing Line 审中-公开
标题翻译：半导体器件制造线
公开(公告)号：US20140119858A1
公开(公告)日：2014-05-01
申请号：US14032041
申请日：2013-09-19
申请人： SANDISK 3D LLC
发明人： Atsuyoshi Koike , Takayuki Wakabayashi , Hideki Kishi
IPC分类号： H01L21/677
CPC分类号： H01L21/67703 , H01L21/6773 , H01L21/67736 , H01L21/67772
摘要： A semiconductor device manufacturing line includes a process system that includes a plurality of process units of a single wafer process type, and a carrier system that carries wafers to the plurality of process units. The carrier system includes a plurality of carrier units each carrying one wafer from one of the process units to another process unit of a next process.
摘要翻译：半导体器件制造线包括包括单个晶片工艺类型的多个处理单元和将晶片运送到多个处理单元的载体系统的处理系统。载体系统包括多个载体单元，每个载体单元将一个晶片从一个处理单元承载到另一个处理单元。

80. 发明申请

US20140117514A1 METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE 有权
标题翻译：自制符号大气记忆结构的制作方法
公开(公告)号：US20140117514A1
公开(公告)日：2014-05-01
申请号：US14140468
申请日：2013-12-24
申请人： SanDisk 3D LLC
发明人： Kang-Jay Hsia , Calvin K. Li , Christopher John Petti
IPC分类号： H01L29/66 , H01L29/868
CPC分类号： H01L29/6609 , H01L21/76802 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
摘要翻译：提供一种形成存储单元的方法。该方法包括：形成包括第一半导体材料的第一柱状元件，形成与第一柱状元件自对准的第一开口，以及在第一开口中沉积第二半导体材料以形成第二柱状元件在第一个柱状元件之上。还提供其他方面。

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