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1. 发明授权

US08980766B2 Sequential atomic layer deposition of electrodes and resistive switching components 有权
标题翻译：电极和电阻式开关元件的顺序原子层沉积
公开(公告)号：US08980766B2
公开(公告)日：2015-03-17
申请号：US14327774
申请日：2014-07-10
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L21/68 , H01L45/00 , H01L27/24
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
摘要翻译：提供了使用原子层沉积技术形成非易失性存储元件的方法，其中存储元件的至少两个不同层顺次沉积并且在沉积室中不破坏真空。该方法可以用于防止用于电极的各种材料的氧化，而不需要单独的氧阻隔层。可以使用信号线和电阻开关层的组合来封盖电极并使其氧化最小化。因此，存储元件中需要更少的层。此外，原子层沉积允许更精确地控制电极厚度。在一些实施例中，电极的厚度可以小于50埃。总的来说，电极和电阻开关层的原子层沉积导致整个存储元件的较小厚度，使得它们更适合于高级节点的低纵横比特征。

2. 发明授权

US08975114B2 Method for forming metal oxides and silicides in a memory device 有权
标题翻译：在存储器件中形成金属氧化物和硅化物的方法
公开(公告)号：US08975114B2
公开(公告)日：2015-03-10
申请号：US13804318
申请日：2013-03-14
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Dipankar Pramanik , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L21/00 , H01L21/16 , H01L45/00 , H01L27/10 , H01L27/24
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
摘要翻译：本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热到约300的范围内的氧化温度约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。下部电极含有硅材料，金属层含有铪或锆。在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层处理。

3. 发明申请

US20150056749A1 Atomic Layer Deposition of Metal Oxide Materials for Memory Applications 有权
标题翻译：用于存储器应用的金属氧化物材料的原子层沉积
公开(公告)号：US20150056749A1
公开(公告)日：2015-02-26
申请号：US14506298
申请日：2014-10-03
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

4. 发明申请

US20140175354A1 SEQUENTIAL ATOMIC LAYER DEPOSITION OF ELECTRODES AND RESISTIVE SWITCHING COMPONENTS 有权
标题翻译：电极和电阻开关元件的顺序原子层沉积
公开(公告)号：US20140175354A1
公开(公告)日：2014-06-26
申请号：US13721549
申请日：2012-12-20
申请人： INTERMOLECULAR INC. , KABUSHIKI KAISHA TOSHIBA , SANDISK 3D LLC
发明人： Yun Wang , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
摘要翻译：提供了使用原子层沉积技术形成非易失性存储元件的方法，其中存储元件的至少两个不同层顺次沉积并且在沉积室中不破坏真空。该方法可以用于防止用于电极的各种材料的氧化，而不需要单独的氧阻隔层。可以使用信号线和电阻开关层的组合来封盖电极并使其氧化最小化。因此，存储元件中需要更少的层。此外，原子层沉积允许更精确地控制电极厚度。在一些实施例中，电极的厚度可以小于50埃。总的来说，电极和电阻开关层的原子层沉积导致整个存储元件的较小厚度，使得它们更适合于高级节点的低纵横比特征。

5. 发明申请

US20140117303A1 Resistive Random Access Memory Cells Having METAL ALLOY Current Limiting layers 有权
公开(公告)号：US20140117303A1
公开(公告)日：2014-05-01
申请号：US13722314
申请日：2012-12-20
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

6. 发明授权

US08652923B2 Nonvolatile memory device having an electrode interface coupling region 有权
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US08652923B2
公开(公告)日：2014-02-18
申请号：US13829194
申请日：2013-03-14
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

7. 发明申请

US20130217179A1 Nonvolatile Memory Device Having An Electrode Interface Coupling Region 有权
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US20130217179A1
公开(公告)日：2013-08-22
申请号：US13829194
申请日：2013-03-14
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

8. 发明授权

US09299928B2 Nonvolatile memory device having a current limiting element 有权
公开(公告)号：US09299928B2
公开(公告)日：2016-03-29
申请号：US14625867
申请日：2015-02-19
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

9. 发明授权

US09184383B2 Nonvolatile memory device having an electrode interface coupling region 有权
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US09184383B2
公开(公告)日：2015-11-10
申请号：US14156762
申请日：2014-01-16
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

10. 发明申请

US20150162530A1 Nonvolatile Memory Device Having a Current Limiting Element 审中-公开
标题翻译：具有限流元件的非易失性存储器件
公开(公告)号：US20150162530A1
公开(公告)日：2015-06-11
申请号：US14625867
申请日：2015-02-19
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。所形成的限流层或电阻层的电性能被配置为在逻辑状态编程步骤（即“设定”和“复位”步骤）期间通过添加固定的串联电阻来降低通过可变电阻层的电流在形成在非易失性存储器件中的电阻式开关存储元件中。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

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