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71. 发明授权

US07514748B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07514748B2
公开(公告)日：2009-04-07
申请号：US11226978
申请日：2005-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DRAM存储器件的半导体器件。半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

72. 发明申请

US20080068882A1 Semiconductor device 审中-公开
公开(公告)号：US20080068882A1
公开(公告)日：2008-03-20
申请号：US11904977
申请日：2007-09-28
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/401
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

73. 发明授权

US07342842B2 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US07342842B2
公开(公告)日：2008-03-11
申请号：US11649945
申请日：2007-01-05
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C7/00 , G11C11/24 , G11C11/34
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元10的DRAM存储器的数据存储装置。每个数据存储单元10具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路16，写入电路18和刷新电路22将输入信号施加到数据存储单元，以通过使代表二进制逻辑状态之一的那些单元的至少那些单元的时间的时间来反转物理参数的变化，在所述状态之一的细胞的物理参数比在另一个状态。

74. 发明申请

US20080025083A1 Bipolar reading technique for a memory cell having an electrically floating body transistor 有权
标题翻译：具有电浮体晶体管的存储单元的双极读取技术
公开(公告)号：US20080025083A1
公开(公告)日：2008-01-31
申请号：US11906036
申请日：2007-09-28
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016 , H01L27/1023 , H01L27/108 , H01L29/78 , H01L29/7841
摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor. In this regard, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating body memory cell. During the read operation, the data state is determined primarily by or read (or sensed) substantially using the bipolar current component responsive to the read control signals and significantly less by the interface channel current component, which is negligible relative to the bipolar component. The bipolar transistor current component may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor of the electrically floating body transistor. As such, the programming window obtainable with this reading technique may be considerably higher than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component).
摘要翻译：一种采样，感测，读取和/或确定包括电浮体晶体管的存储单元（例如，存储单元阵列）的数据状态的技术。在这方面，使用本征双极晶体管电流分量来读取和/或确定电浮体存储单元的数据状态。在读取操作期间，数据状态主要由读取的控制信号基本上使用双极电流分量或相对于双极组件可忽略的界面通道电流分量来显着地（或感测到的）来确定或读取（或感测到的）数据状态。由于电浮体晶体管的本征双极晶体管的高增益，双极晶体管电流分量可能对浮体电位非常敏感。因此，利用该读取技术可获得的编程窗口可以比使用常规读取技术（其主要基于接口通道电流分量）的编程窗口高得多。

75. 发明授权

US07184298B2 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
标题翻译：用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术
公开(公告)号：US07184298B2
公开(公告)日：2007-02-27
申请号：US10941692
申请日：2004-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/24 , H01L27/01
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储器单元的电流/功耗很少电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

76. 发明申请

US20070023833A1 Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same 审中-公开
标题翻译：用于读取具有电浮体晶体管的存储单元的方法，以及实现其的存储单元和阵列
公开(公告)号：US20070023833A1
公开(公告)日：2007-02-01
申请号：US11453594
申请日：2006-06-15
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： H01L27/12
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/785
摘要： An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. Circuitry, coupled to the electrically floating body transistor of the memory cell, (i) generates read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation. The electrically floating body transistor may be disposed on a bulk-type substrate or SOI-type substrate.
摘要翻译：一种集成电路器件（例如，逻辑或分立存储器件），包括一个包括一电浮体晶体管的存储单元，其中该电浮体晶体管包括一源极区，一漏极区，置于源区和漏极区域，其中所述体区域是电浮动的，以及设置在所述身体区域上的栅极。存储单元包括（i）代表电浮体晶体管的体区中的第一电荷的第一数据状态，和（ii）代表在电浮体晶体管的体区中的第二电荷的第二数据状态电浮体晶体管。电路，耦合到存储单元的电浮体晶体管，（i）产生读控制信号以执行存储单元的读操作，和（ii）将读控制信号施加到电浮体晶体管以感测数据状态的记忆单元; 其中，响应于读取控制信号，电浮动体晶体管在读操作期间补充电浮体晶体管的体区中的电荷。电浮体晶体管可以设置在体型衬底或SOI型衬底上。

77. 发明授权

US07061050B2 Semiconductor device utilizing both fully and partially depleted devices 失效
标题翻译：利用全部和部分耗尽的器件的半导体器件
公开(公告)号：US07061050B2
公开(公告)日：2006-06-13
申请号：US10487157
申请日：2003-03-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semi-conductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DPAM存储器件的半导体器件。 A，半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

78. 发明申请

US20060098481A1 Circuitry for and method of improving statistical distribution of integrated circuits 有权
标题翻译：提高集成电路统计分布的电路及方法
公开(公告)号：US20060098481A1
公开(公告)日：2006-05-11
申请号：US11247774
申请日：2005-10-11
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/4076 , G11C7/1045 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/2254 , G11C2211/4016
摘要： An integrated circuit device comprising a memory array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating and a gate disposed over the body region and separated therefrom by a gate dielectric. Each memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the gate. The integrated circuit device further includes operating characteristics adjustment circuitry, coupled to the memory cell array, to responsively adjust one or more operating or response characteristics of one or more predetermined memory cells and thereby enhance the uniformity of operation or response of the predetermined memory cells of the memory array relative to the plurality of memory cells of the memory array.
摘要翻译：一种集成电路装置，包括包括多个存储单元的存储器阵列，其中每个存储单元包括至少一个具有源极区，漏极区，设置在源区和漏区之间的体区的电浮体晶体管，其中，身体区域是电浮动的，并且栅极设置在身体区域上并由栅极电介质分离。每个存储单元包括表示体区中的第一电荷的第一数据状态和代表体区中的第二电荷的第二数据状态，其中第二电荷基本上通过从门体去除身体区域的电荷来提供。集成电路装置还包括耦合到存储器单元阵列的操作特性调整电路，以响应地调整一个或多个预定存储器单元的一个或多个操作或响应特性，从而增强预定存储器单元的操作或响应的均匀性存储器阵列相对于存储器阵列的多个存储器单元。

79. 发明申请

US20060006468A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060006468A1
公开(公告)日：2006-01-12
申请号：US11226978
申请日：2005-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L27/01
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DRAM存储器件的半导体器件。半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

80. 发明申请

US20050213379A1 Semiconductor device 有权
公开(公告)号：US20050213379A1
公开(公告)日：2005-09-29
申请号：US11132979
申请日：2005-05-19
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C11/34
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

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