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1. 发明申请

US20120273888A1 SEMICONDUCTOR DEVICE WITH ELECTRICALLY FLOATING BODY 有权
标题翻译：具有电动浮体的半导体器件
公开(公告)号：US20120273888A1
公开(公告)日：2012-11-01
申请号：US13547717
申请日：2012-07-12
申请人： Serguei OKHONIN
发明人： Serguei OKHONIN
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1203 , G11C7/00 , G11C11/40 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该装置包括电浮体区域，并且栅极设置在身体区域的第一部分之上。该装置包括与该区域的第二部分邻接的源极区域，该第二部分与该第一部分相邻并且将该源区域与该第一部分分开。该装置包括与该区域的第三部分邻接的漏极区域，该第三部分与该第一部分相邻并且将该漏极区域与该第一部分分开。

2. 发明申请

US20120236671A1 REFRESHING DATA OF MEMORY CELLS WITH ELECTRICALLY FLOATING BODY TRANSISTORS 有权
标题翻译：用电浮动体晶体管刷新记忆细胞数据
公开(公告)号：US20120236671A1
公开(公告)日：2012-09-20
申请号：US13479065
申请日：2012-05-23
申请人： Eric CARMAN , Mikhail NAGOGA , Serguei OKHONIN
发明人： Eric CARMAN , Mikhail NAGOGA , Serguei OKHONIN
IPC分类号： G11C11/402
CPC分类号： G11C11/4096 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括一个包括一个晶体管的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

3. 发明授权

US07933142B2 Semiconductor memory cell and array using punch-through to program and read same 有权
标题翻译：半导体存储单元和阵列使用穿通来编程和读取相同
公开(公告)号：US07933142B2
公开(公告)日：2011-04-26
申请号：US11796935
申请日：2007-04-30
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.
摘要翻译：一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体，以及一个具有存储节点至少部分地位于栅极绝缘体的正下方。存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。晶体管可以设置在体型衬底或SOI型衬底上。

4. 发明申请

US20100277982A1 SEMICONDUCTOR DEVICE WITH FLOATING GATE AND ELECTRICALLY FLOATING BODY 有权
标题翻译：具有浮动门和电动浮动体的半导体器件
公开(公告)号：US20100277982A1
公开(公告)日：2010-11-04
申请号：US12770249
申请日：2010-04-29
申请人： Serguei OKHONIN
发明人： Serguei OKHONIN
IPC分类号： G11C14/00 , H01L27/108 , H01L21/336
CPC分类号： H01L29/788 , G11C11/404 , G11C14/0018 , G11C16/0408 , G11C16/0416 , G11C16/12 , G11C16/26 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7885 , H01L29/792
摘要： Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.
摘要翻译：公开了用于提供浮体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括浮置栅极，设置在浮置栅极上的控制栅极，电浮置的主体区域的半导体器件，其中，主体区域被配置为使得形成主体区域被包含在浮置栅极的至少一个横向边界下方，以及与该区域相邻的源极区域和漏极区域。

5. 发明授权

US07606066B2 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same 有权
标题翻译：具有电浮体晶体管的存储单元和存储单元阵列及其操作方法
公开(公告)号：US07606066B2
公开(公告)日：2009-10-20
申请号：US11509188
申请日：2006-08-24
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/409 , G11C11/404 , G11C11/4067 , G11C11/4076 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
摘要翻译：写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术）电浮体晶体管）。一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，该半导体存储单元具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

6. 发明申请

US20070159911A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070159911A1
公开(公告)日：2007-07-12
申请号：US11713284
申请日：2007-03-02
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列的矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

7. 发明授权

US07187581B2 Semiconductor memory device and method of operating same 有权
公开(公告)号：US07187581B2
公开(公告)日：2007-03-06
申请号：US11079590
申请日：2005-03-14
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

8. 发明授权

US07177175B2 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
公开(公告)号：US07177175B2
公开(公告)日：2007-02-13
申请号：US11334338
申请日：2006-01-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/24 , H01L27/01
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

9. 发明授权

US06925006B2 Semiconductor device 有权
公开(公告)号：US06925006B2
公开(公告)日：2005-08-02
申请号：US10724377
申请日：2003-11-28
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

10. 发明授权

US08508994B2 Semiconductor device with floating gate and electrically floating body 有权
标题翻译：具有浮动栅极和电浮体的半导体器件
公开(公告)号：US08508994B2
公开(公告)日：2013-08-13
申请号：US12770249
申请日：2010-04-29
申请人： Serguei Okhonin
发明人： Serguei Okhonin
IPC分类号： G11C14/00
CPC分类号： H01L29/788 , G11C11/404 , G11C14/0018 , G11C16/0408 , G11C16/0416 , G11C16/12 , G11C16/26 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7885 , H01L29/792
摘要： Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.
摘要翻译：公开了用于提供浮体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括浮置栅极，设置在浮置栅极上的控制栅极，电浮置的主体区域的半导体器件，其中，主体区域被配置为使得形成主体区域被包含在浮置栅极的至少一个横向边界下方，以及与该区域相邻的源极区域和漏极区域。

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