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1. 发明授权

US08329574B2 Methods of fabricating flash memory devices having shared sub active regions 有权
标题翻译：制造具有共享子有源区的闪存器件的方法
公开(公告)号：US08329574B2
公开(公告)日：2012-12-11
申请号：US13230978
申请日：2011-09-13
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

2. 发明授权

US08217427B2 High density stable static random access memory 有权
标题翻译：高密度稳定的静态随机存取存储器
公开(公告)号：US08217427B2
公开(公告)日：2012-07-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有较薄的掩埋氧化物层。

3. 发明申请

US20120119291A1 Power device with self-aligned source regions 有权
标题翻译：具有自对准源区的功率器件
公开(公告)号：US20120119291A1
公开(公告)日：2012-05-17
申请号：US13270050
申请日：2011-10-10
申请人： Robert Herrick , Becky Losee , Dean Probst
发明人： Robert Herrick , Becky Losee , Dean Probst
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/7802 , Y10S257/905
摘要： A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.
摘要翻译：场效应晶体管（FET）包括延伸到硅层的多个沟槽，每个沟槽具有扇出的上侧壁。接触开口延伸到相邻沟槽之间的硅层中，使得每个沟槽和相邻的接触开口形成共同的上侧壁部分。主体区域在相邻沟槽之间延伸。与对应的沟槽自对准的源极区域在与每个沟槽的相对侧壁相邻的主体区域中延伸，并且具有与身体区域相反的导电类型。

4. 发明申请

US20110042742A1 STRUCTURES OF AND METHODS OF FABRICATING TRENCH-GATED MIS DEVICES 审中-公开
标题翻译：制造TRENCH-GATED MIS装置的结构和方法
公开(公告)号：US20110042742A1
公开(公告)日：2011-02-24
申请号：US12917378
申请日：2010-11-01
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

5. 发明授权

US07750962B2 Device for subtracting or adding charge in a charge-coupled device 失效
标题翻译：用于在电荷耦合器件中减去或增加电荷的装置
公开(公告)号：US07750962B2
公开(公告)日：2010-07-06
申请号：US11676640
申请日：2007-02-20
申请人： Michael P. Anthony
发明人： Michael P. Anthony
IPC分类号： H04N3/14 , H01L27/148
CPC分类号： H04N5/347 , H04N5/372 , Y10S257/905
摘要： The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.
摘要翻译：本发明提供了一种用于在数据包穿过CCD时向CCD中的电荷分组加或减量量的装置。该装置使用“有线传输”装置结构来在充电数据包遍历装置期间执行电荷的加或减。一对电互连的扩散结合在电荷耦合路径内，以提供当分组穿过CCD时能从分组中加或减的电荷量。

6. 发明授权

US07745279B2 Capacitor that includes high permittivity capacitor dielectric 有权
标题翻译：包括高介电常数电容器电容器的电容器
公开(公告)号：US07745279B2
公开(公告)日：2010-06-29
申请号：US11331703
申请日：2006-01-13
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/8242
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括硅表面层的半导体衬底上形成去耦电容器。在半导体表面层的一部分中形成基本平坦的底部电极。电容器电介质覆盖在底部电极上。电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

7. 发明授权

US07723776B2 Flash memory devices having shared sub active regions 有权
标题翻译：具有共享子活动区域的闪存设备
公开(公告)号：US07723776B2
公开(公告)日：2010-05-25
申请号：US11376371
申请日：2006-03-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

8. 发明授权

US07704825B2 Method of fabricating memory including diode 有权
标题翻译：制造二极管存储器的方法
公开(公告)号：US07704825B2
公开(公告)日：2010-04-27
申请号：US12149137
申请日：2008-04-28
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： H01L21/8239 , H01L21/8246 , H01L21/8234 , H01L27/10 , H01L27/112 , H01L27/105
CPC分类号： H01L27/11253 , G11C11/15 , G11C17/06 , H01L27/105 , H01L27/112 , H01L27/11213 , H01L27/11293 , H01L27/224 , Y10S257/903 , Y10S257/905 , Y10S257/909 , Y10S257/91
摘要： A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.
摘要翻译：提供了能够减小存储单元大小的存储器。该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区，以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

9. 发明授权

US07649259B2 Semiconductor device including a plurality of wiring lines 失效
标题翻译：包括多条布线的半导体装置
公开(公告)号：US07649259B2
公开(公告)日：2010-01-19
申请号：US11316887
申请日：2005-12-27
申请人： Mizuki Ono , Yuichi Motoi
发明人： Mizuki Ono , Yuichi Motoi
IPC分类号： H01L23/52
CPC分类号： H01L27/101 , H01L27/105 , Y10S257/905 , Y10S257/908
摘要： A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.
摘要翻译：半导体器件包括由金属构成的第一布线线组，第一布线线组的布线彼此平行布置，第二布线线组由半导体制成并与第一布线组交叉，布线第二布线线组的线相互平行配置，并且能够在与第一布线线组的布线相交的各交点附近移动，并且形成为与布线接合的多个金属区构成第二配线组，并且具有与形成第一配线组的金属不同的功函数。

10. 发明授权

US07595524B2 Power device with trenches having wider upper portion than lower portion 有权
标题翻译：具有沟槽的功率器件具有比下部更宽的上部部分
公开(公告)号：US07595524B2
公开(公告)日：2009-09-29
申请号：US12049996
申请日：2008-03-17
申请人： Robert Herrick , Becky Losee , Dean Probst
发明人： Robert Herrick , Becky Losee , Dean Probst
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/7802 , Y10S257/905
摘要： A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.
摘要翻译：场效应晶体管包括延伸到硅层的多个沟槽。每个沟槽具有扇出的上侧壁。接触开口延伸到相邻沟槽之间的硅层中，使得每个沟槽和相邻的接触开口形成共同的上侧壁部分。主体区域在相邻沟槽之间延伸，并且源区域在与每个沟槽的相对侧壁相邻的主体区域中延伸。源区具有与体区相反的导电性。

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