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71. 发明授权

US09012274B2 Method of manufacturing a semiconductor fin using sacrificial layer 有权
标题翻译：使用牺牲层制造半导体翅片的方法
公开(公告)号：US09012274B2
公开(公告)日：2015-04-21
申请号：US13580965
申请日：2012-05-14
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L21/20 , H01L27/12 , H01L29/06 , H01L29/66
CPC分类号： H01L21/20 , H01L27/1211 , H01L29/0657 , H01L29/66795
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming an insulating film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, an oxide film is formed on the sidewalls of the two semiconductor fins that are far away from each other, while only the sidewalls of the two semiconductor fins that are opposite to each other are exposed, such that conventional operations may be easily performed to the sidewalls opposite to each other in the subsequent process.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在半导体主体的侧壁上形成绝缘膜; 去除位于牺牲层下方的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片。相应地，本发明还提供一种半导体结构。在本发明中，在远离彼此的两个半导体翅片的侧壁上形成氧化膜，只有两个相互相对的两个半导体翅片的侧壁露出，这样常规的操作可以是在随后的过程中容易地对彼此相对的侧壁进行。

72. 发明申请

US20140362652A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME 有权
标题翻译：半导体存储器件及其接收方法
公开(公告)号：US20140362652A1
公开(公告)日：2014-12-11
申请号：US14355120
申请日：2012-03-22
申请人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/105 , H01L29/267 , G11C7/00 , H01L29/786
CPC分类号： H01L27/1052 , G11C5/06 , G11C7/00 , G11C8/16 , G11C11/404 , G11C11/405 , H01L27/108 , H01L29/267 , H01L29/7869
摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.
摘要翻译：公开了一种半导体存储器件及其访问方法。半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。半导体存储器件增加了集成度并降低了刷新频率。

73. 发明授权

US08889554B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08889554B2
公开(公告)日：2014-11-18
申请号：US13380486
申请日：2011-04-18
申请人： Haizhou Yin , Wei Jiang , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Wei Jiang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/41775 , H01L29/456 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：在第一间隔物的暴露的有源区上形成第一接触层; 在所述第一接触层的靠近栅极堆叠的区域处形成第二间隔物以部分地覆盖所述暴露的有源区; 在未覆盖的暴露的有源区中形成第二接触层，其中当第一接触层的扩散系数与第二接触层的扩散系数相同时，第一接触层的厚度小于第二接触层的厚度; 并且当第一接触层的扩散系数与第二接触层的扩散系数不同时，第一接触层的扩散系数小于第二接触层的扩散系数。相应地，本发明还提供一种半导体结构。本发明有利于抑制相应组合物从接触层扩散到沟道区中，减少短沟道效应，提高半导体结构的可靠性。

74. 发明授权

US08878280B2 Flash memory device and method for manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US08878280B2
公开(公告)日：2014-11-04
申请号：US13148265
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L27/115 , H01L29/66 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L27/11521 , H01L29/66803 , H01L29/66825 , H01L29/7881
摘要： The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.
摘要翻译：本发明提供一种FinFET闪速存储器件及其制造方法。闪存器件在绝缘层上，包括：第一鳍片和第二鳍片，其中第二鳍片是器件的控制栅极; 栅极电介质层，位于第一鳍片和第二鳍片的侧壁和顶部; 源极/漏极区域，位于浮动栅极两侧的第一鳍片内。

75. 发明申请

US20140225200A1 Enhancing MOSFET Performance With Corner Stresses of STI 有权
标题翻译：通过STI的角应力提高MOSFET性能
公开(公告)号：US20140225200A1
公开(公告)日：2014-08-14
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

76. 发明授权

US08803208B2 Method for fabricating contact electrode and semiconductor device 有权
标题翻译：接触电极和半导体器件的制造方法
公开(公告)号：US08803208B2
公开(公告)日：2014-08-12
申请号：US13129075
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/485 , H01L29/66 , H01L29/417
CPC分类号： H01L23/485 , H01L29/41775 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.
摘要翻译：本发明提供了一种半导体器件，包括：衬底; 形成在基板上的栅极; 源极和漏极分别位于栅极的相对侧上; 接触件，其与源极和/或漏极接触，其中接触件在与源极和/或漏极接触的端部处具有扩大的端部。在本发明中，由于在与源极/漏极接触的界面上接触面的接触面积增加，所以可以降低接触电阻，能够保证/提高半导体器件的性能。本发明还提供如前所述制造半导体器件（特别是其中的接触）的方法。

77. 发明授权

US08742545B2 Substrate strip plate structure for semiconductor device and method of manufacturing the same 有权
标题翻译：用于半导体器件的基板带状板结构及其制造方法
公开(公告)号：US08742545B2
公开(公告)日：2014-06-03
申请号：US13264063
申请日：2010-04-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： A strip plate structure and a method of manufacturing the same are disclosed. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing. Each of the strip plates includes a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets. Each strip sheet alternately abuts either the first surfaces or the second surfaces of two adjacent strip plates.
摘要翻译：公开了一种带状板结构及其制造方法。在一个实施例中，带状板结构包括带板阵列，其包括以预定方向间隔布置的多个带状板。每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向带状板结构的基本相反的侧面方向的第二表面; 和多个条状片。每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

78. 发明授权

US08722524B2 Method for forming a semiconductor device including replacing material of dummy gate stacks with other conductive material 有权
标题翻译：用于形成半导体器件的方法，包括用其它导电材料代替伪栅极堆叠的材料
公开(公告)号：US08722524B2
公开(公告)日：2014-05-13
申请号：US13380362
申请日：2011-02-27
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823418 , H01L29/49 , H01L29/66545 , H01L29/7833
摘要： It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.
摘要翻译：提供一种用于形成半导体器件的方法，包括：形成暴露伪栅极和侧壁间隔物并填充两个相邻栅极堆叠之间的空间的材料层，并且材料层的材料与虚拟栅极的材料相同; 去除虚拟门和材料层以形成凹槽; 用导电材料填充凹部，并平坦化导电材料以暴露侧壁间隔物; 将导电材料破坏在侧壁间隔物外部以形成至少两个导体，每个导体仅在侧壁间隔件之外的一侧处与有源区域接触，以便形成栅叠层结构和第一触点。此外，提供了半导体器件。该方法和半导体器件有利于在形成触点时延长工艺窗口。

79. 发明申请

US20140124859A1 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140124859A1
公开(公告)日：2014-05-08
申请号：US13380857
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/28 , H01L29/78 , H01L29/423
CPC分类号： H01L21/28008 , H01L29/41733 , H01L29/4232 , H01L29/66545 , H01L29/66643 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method. The manufacturing method and the semiconductor structure according to the present invention make it possible to reduce capacitance between a metal layer and a body silicon layer of an SOI substrate when a semiconductor device is in operation, which is therefore favorable for enhancing performance of the semiconductor device.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和SOI衬底的BOX层以形成沟槽，沟槽暴露BOX层并部分延伸到BOX层中; 在沟槽的侧壁上形成侧壁间隔物; 在所述沟槽内部形成覆盖所述侧壁间隔物的金属层，其中所述金属层与所述栅极结构下方的所述SOI层接触。因此，本发明还提供根据上述方法形成的半导体结构。根据本发明的制造方法和半导体结构使半导体器件工作时能够减小SOI衬底的金属层与体硅层之间的电容，因此有利于提高半导体器件的性能。

80. 发明授权

US08673704B2 FinFET and method for manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US08673704B2
公开(公告)日：2014-03-18
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

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