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71. 发明申请

US20130339571A1 3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF 有权
标题翻译：具有垂直位线和立柱字线和垂直开关的3D存储器及其方法
公开(公告)号：US20130339571A1
公开(公告)日：2013-12-19
申请号：US13835032
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea , Roy E. Scheuerlein
IPC分类号： G06F12/02
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
摘要翻译：具有垂直局部位线的3D存储器全局位线具有形成为垂直结构的薄膜晶体管（TFT）形式的在线垂直开关，以将局部位线切换到全局位线。 TFT被实现为通过强耦合的选择栅极来切换局部位线所承载的最大电流，该选择栅极必须装配在局部位线周围的空间内。选择栅极的最大厚度是通过选择栅极实现的，该选择栅极从局部位线的两侧专门占据x方向的空间。该行的奇数和偶数位线的开关在z方向上交错和偏移，使得偶数和奇数局部位线的选择栅极沿x方向不重合。通过环绕选择门进一步增强切换。

72. 发明申请

US20130313509A1 Bipolar Multistate Nonvolatile Memory 有权
公开(公告)号：US20130313509A1
公开(公告)日：2013-11-28
申请号：US13953296
申请日：2013-07-29
申请人： Intermolecular Inc. , SanDisk 3D LLC , Kabushiki Kaisha Toshiba
发明人： Tony P. Chiang
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616
摘要： Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

73. 发明授权

US08575715B2 Punch-through diode steering element 有权
标题翻译：穿通二极管转向元件
公开(公告)号：US08575715B2
公开(公告)日：2013-11-05
申请号：US13571100
申请日：2012-08-09
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L29/66
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

74. 发明授权

US08557685B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08557685B2
公开(公告)日：2013-10-15
申请号：US12536463
申请日：2009-08-05
申请人： Huiwen Xu
发明人： Huiwen Xu
IPC分类号： H01L21/20 , H01L47/00
CPC分类号： H01L27/101 , G11C2213/35 , G11C2213/71 , H01L21/3146 , H01L21/318 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by (a) depositing a layer of the carbon material above a substrate; (b) doping the deposited carbon layer with a dopant; (c) depositing a layer of the carbon material over the doped carbon layer; and (d) iteratively repeating steps (b) and (c) to form a stack of doped carbon layers having a desired thickness. Other aspects are also provided.
摘要翻译：提供了存储单元和形成这种存储单元的方法，其包括碳基可逆电阻率切换材料。在特定实施例中，根据本发明的方法通过以下步骤形成存储器单元：（a）在基底上沉积碳材料层; （b）用掺杂剂掺杂沉积的碳层; （c）在所述掺杂碳层上沉积所述碳材料层; 和（d）重复地重复步骤（b）和（c）以形成具有期望厚度的掺杂碳层的堆叠。还提供其他方面。

75. 发明授权

US08553476B2 Three dimensional memory system with page of data across word lines 有权
标题翻译：三维存储系统，具有跨字线的数据页面
公开(公告)号：US08553476B2
公开(公告)日：2013-10-08
申请号：US13039581
申请日：2011-03-03
申请人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
发明人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C2213/33 , G11C2213/35 , G11C2213/71
摘要： A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.
摘要翻译：非易失性存储元件的三维单片存储器阵列包括多个字线和多个位线。多个位线被分组成列。通过编程连接到一列位线和多个字线的非易失性存储元件，同时保持对一列位线的选择，一页数据被存储在多个字线上。在一个实施例中，编程非易失性存储元件包括使用包括存储设备，连接到存储设备的选择电路和提供两个或更多个接口的各个选择的一个或多个电平移位器的选择电路选择性地将位线连接到读出放大器电路。

76. 发明授权

US08551850B2 Methods of forming a reversible resistance-switching metal-insulator-metal structure 有权
标题翻译：形成可逆电阻切换金属 - 绝缘体 - 金属结构的方法
公开(公告)号：US08551850B2
公开(公告)日：2013-10-08
申请号：US12631913
申请日：2009-12-07
申请人： Yubao Li , Chu-Chen Fu , Jingyan Zhang
发明人： Yubao Li , Chu-Chen Fu , Jingyan Zhang
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , G11C13/025 , H01L27/2409 , H01L27/2481 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1691
摘要： A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided.
摘要翻译：提供一种形成可逆电阻切换金属 - 绝缘体 - 金属结构的方法，该方法包括形成第一非金属导电层，在第一非金属导电层上方形成非导电层，形成第二非金属导电层，在非导电层之上的金属导电层，蚀刻第一非金属导电层，非导电层和第二非金属导电层以形成柱，以及在柱的侧壁周围设置碳材料层。还提供其他方面。

77. 发明授权

US08547720B2 Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines 有权
标题翻译：具有读/写元素的3D阵列的非易失性存储器，其具有垂直位线和字线的有效解码
公开(公告)号：US08547720B2
公开(公告)日：2013-10-01
申请号：US13151224
申请日：2011-06-01
申请人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
发明人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
IPC分类号： G11C5/02
CPC分类号： G11C16/10 , G11C13/003 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/149
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括从基板到多层平面的两列立柱阵列。第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。第二组柱线连接到字线。衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。

78. 发明申请

US20130234099A1 NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有金属氧化物切换元件的非挥发性储存及其制造方法
公开(公告)号：US20130234099A1
公开(公告)日：2013-09-12
申请号：US13848603
申请日：2013-03-21
申请人： SANDISK 3D LLC
发明人： Deepak C. Sekar , Franz Kreupl , Raghuveer S. Makala , Peter Rabkin , Chu-Chen Fu , Tong Zhang
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1641 , H01L45/1675
摘要： Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide.
摘要翻译：本文公开了具有可逆电阻率开关元件的非易失性存储元件及其制造技术。可逆电阻率开关元件可以通过在顶部电极上沉积防氧扩散材料（例如，重掺杂的Si，W，WN）来形成。可以将陷阱钝化材料（例如，氟，氮，氢，氘）并入到可逆电阻率切换元件的底部电极，金属氧化物区域或顶部电极中的一个或多个中。一个实施例包括在金属氧化物和顶部电极之间具有双层覆盖层的可逆电阻率开关元件。制造该器件可以包括沉积（未反应的）钛并原位沉积二氧化钛而没有空气破裂。一个实施例包括将钛结合到可逆电阻率开关元件的金属氧化物中。可以在沉积金属氧化物的同时或在沉积金属氧化物之后将钛注入金属氧化物中。

79. 发明授权

US08530318B2 Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same 有权
标题翻译：使用在底部导体上形成的选择性制造的碳纳米管可逆电阻切换元件的记忆单元及其形成方法
公开(公告)号：US08530318B2
公开(公告)日：2013-09-10
申请号：US12410789
申请日：2009-03-25
申请人： April D. Schricker
发明人： April D. Schricker
IPC分类号： H01L21/8222
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L51/0048 , H01L51/0575
摘要： In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.
摘要翻译：在一些方面，提供一种制造存储单元的方法，其包括：（1）在衬底之上制造第一导体; （2）通过以下步骤选择性地制造第一导体上方的碳纳米管（“CNT”）材料：（a）在第一导体上制造CNT籽晶层，其中CNT籽晶层包括硅 - 锗（“Si / Ge” ），（b）平坦化沉积的CNT籽晶层的表面，和（c）在CNT籽晶层上选择性地制造CNT材料; （3）在CNT材料之上制造二极管; 和（4）在二极管上方制造第二导体。提供了许多其他方面。

80. 发明申请

US20130229846A1 Memories with Cylindrical Read/Write Stacks 有权
标题翻译：具有圆柱读/写堆栈的记忆体
公开(公告)号：US20130229846A1
公开(公告)日：2013-09-05
申请号：US13789375
申请日：2013-03-07
申请人： SANDISK 3D LLC
发明人： Henry Chien , Yao-Sheng Lee , George Samachisa , Johann Alsmeier
IPC分类号： G11C5/02 , H01L21/82
CPC分类号： B42D15/02 , A63F13/00 , G11C5/02 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/82 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1616
摘要： A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.
摘要翻译：三维存储器形成为跨越位于半导体衬底上方不同距离的多个层的存储元件的阵列。形成存储元件的圆柱形堆叠，其中圆柱形开口具有沿其壁沉积的读/写材料，以及沿其中心轴线形成的圆柱形垂直位线。形成在这种气缸两侧的记忆元件可以包括延伸到读/写材料中的片电极。

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