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1. 发明授权

US08982597B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08982597B2
公开(公告)日：2015-03-17
申请号：US13362320
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C16/24 , G11C13/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

2. 发明授权

US08351236B2 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture 有权
公开(公告)号：US08351236B2
公开(公告)日：2013-01-08
申请号：US12748260
申请日：2010-03-26
申请人： Tianhong Yan , George Samachisa
发明人： Tianhong Yan , George Samachisa
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/06035 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C16/10 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/71 , G11C2213/75 , G11C2213/78 , H01L23/528 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

3. 发明授权

US08279650B2 Memory system with data line switching scheme 有权
标题翻译：具有数据线切换方案的存储系统
公开(公告)号：US08279650B2
公开(公告)日：2012-10-02
申请号：US12563139
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C5/06
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

4. 发明申请

US20120224408A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 有权
标题翻译：具有柱管的三维存储系统
公开(公告)号：US20120224408A1
公开(公告)日：2012-09-06
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

5. 发明授权

US08130528B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08130528B2
公开(公告)日：2012-03-06
申请号：US12410648
申请日：2009-03-25
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。块被分组成海湾。存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

6. 发明授权

US08098511B2 Reverse set with current limit for non-volatile storage 有权
标题翻译：反向设置为非易失性存储的电流限制
公开(公告)号：US08098511B2
公开(公告)日：2012-01-17
申请号：US12963540
申请日：2010-12-08
申请人： Roy E. Scheuerlein , Tianhong Yan
发明人： Roy E. Scheuerlein , Tianhong Yan
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。存储器单元以反向偏置的方式被设置。

7. 发明申请

US20110305071A1 CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的连续编程
公开(公告)号：US20110305071A1
公开(公告)日：2011-12-15
申请号：US13217235
申请日：2011-08-24
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

8. 发明授权

US08027209B2 Continuous programming of non-volatile memory 有权
标题翻译：连续编程非易失性存储器
公开(公告)号：US08027209B2
公开(公告)日：2011-09-27
申请号：US12563140
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C7/22
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

9. 发明申请

US20100085822A1 CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的连续编程
公开(公告)号：US20100085822A1
公开(公告)日：2010-04-08
申请号：US12563140
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

10. 发明申请

US20100046267A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
标题翻译：具有数据线的存储系统
公开(公告)号：US20100046267A1
公开(公告)日：2010-02-25
申请号：US12410648
申请日：2009-03-25
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C8/00 , G11C5/06
CPC分类号： G11C16/24 , G11C13/0028
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。块被分组成海湾。存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

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