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1. 发明授权

US08575715B2 Punch-through diode steering element 有权
标题翻译：穿通二极管转向元件
公开(公告)号：US08575715B2
公开(公告)日：2013-11-05
申请号：US13571100
申请日：2012-08-09
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L29/66
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

2. 发明授权

US08514629B2 Method for memory cell erasure with a programming monitor of reference cells 有权
标题翻译：用参考单元的编程监视器进行存储单元擦除的方法
公开(公告)号：US08514629B2
公开(公告)日：2013-08-20
申请号：US13602762
申请日：2012-09-04
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

3. 发明授权

US08395942B2 Junctionless TFT NAND flash memory 有权
标题翻译：无结点TFT NAND闪存
公开(公告)号：US08395942B2
公开(公告)日：2013-03-12
申请号：US12848458
申请日：2010-08-02
申请人： George Samachisa , Johann Alsmeier , Andrei Mihnea
发明人： George Samachisa , Johann Alsmeier , Andrei Mihnea
IPC分类号： G11C11/34 , H01L29/06 , H01L29/76
CPC分类号： H01L27/1214 , B82Y10/00 , G11C16/0483 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/112 , H01L27/11206 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method of making a NAND string includes forming a semiconductor layer over a major surface of a substrate, patterning the semiconductor layer into an elongated nanowire shaped channel extending substantially parallel to the major surface of the substrate, forming a tunneling dielectric layer over the channel, forming a plurality of charge storage regions over the tunneling dielectric layer and undercutting the channel using the plurality of charge storage regions as mask. The channel has a narrower width than each charge storage region width, and an overhanging portion of each of the plurality of charge storage regions overhangs the channel. The method also includes forming a blocking dielectric layer over the plurality of charge storage regions, such that the blocking dielectric layer fills a space below the overhanging portion of each of the plurality of charge storage regions and forming a plurality of control gates over the blocking dielectric layer.
摘要翻译：制造NAND串的方法包括在衬底的主表面上形成半导体层，将半导体层图案化成基本上平行于衬底的主表面延伸的细长的纳米线形状的沟道，在沟道上形成隧穿介电层，在隧道电介质层上形成多个电荷存储区域，并使用多个电荷存储区域作为掩模来对沟道进行底切。通道具有比每个电荷存储区域宽度窄的宽度，并且多个电荷存储区域中的每一个的悬伸部分悬垂在通道上。该方法还包括在多个电荷存储区域上形成阻挡电介质层，使得阻挡介电层填充多个电荷存储区域中的每一个的悬垂部分下面的空间，并在阻挡电介质上形成多个控制栅极层。

4. 发明授权

US07924623B2 Method for memory cell erasure with a programming monitor of reference cells 有权
标题翻译：用参考单元的编程监视器进行存储单元擦除的方法
公开(公告)号：US07924623B2
公开(公告)日：2011-04-12
申请号：US12127415
申请日：2008-05-27
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

5. 发明申请

US20100165747A1 NON-VOLATILE MEMORY CELL HEALING 有权
标题翻译：非易失性记忆细胞治疗
公开(公告)号：US20100165747A1
公开(公告)日：2010-07-01
申请号：US12721165
申请日：2010-03-10
申请人： Andrei Mihnea , William Kueber , Mark Helm
发明人： Andrei Mihnea , William Kueber , Mark Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
摘要翻译：本公开的实施例提供了用于治疗非易失性存储器单元的方法，装置，模块和系统。一种方法包括以第一电压偏置耦合到一串存储器单元的第一选择栅极晶体管，以第二电压偏置耦合到串的第二选择栅极晶体管，将第一愈合电压施加到第一边缘字线，以便提取在第一选择栅极晶体管和串的第一边缘存储单元堆之间累积的电荷，以及向第二边缘字线施加第二愈合电压，以便提取在第二选择栅极晶体管和第二边缘存储单元之间累积的电荷堆栈的字符串。

6. 发明授权

US07639530B2 Method for programming and erasing an NROM cell 有权
标题翻译：编程和擦除NROM单元的方法
公开(公告)号：US07639530B2
公开(公告)日：2009-12-29
申请号：US11599701
申请日：2006-11-15
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/10
摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.
摘要翻译：氮化物只读存储器（NROM）单元可以通过向栅极输入施加斜坡电压，对两个源极/漏极区中的一个施加恒定电压，并将剩余的源极/漏极区的接地电位编程。为了擦除NROM单元，将恒定电压耦合到栅极输入端。恒定的正电流被输入到源/漏区之一。剩余的源极/漏极区域被允许浮动，耦合到接地电位，或耦合到第一源极/漏极区域。

7. 发明申请

US20090003065A1 Flash cell with improved program disturb 审中-公开
标题翻译：闪存单元具有改进的程序干扰
公开(公告)号：US20090003065A1
公开(公告)日：2009-01-01
申请号：US11821915
申请日：2007-06-26
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： H01L29/788 , G11C11/34 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42324
摘要： Memory cells, memory arrays, memory devices and methods are disclosed, such as those involving a memory cell comprising a floating gate comprising lightly doped polysilicon, wherein the lightly doped polysilicon has a substantially uniform doping concentration. One such memory cell further comprises a control gate and dielectric disposed between the floating gate and the control gate.
摘要翻译：公开了存储器单元，存储器阵列，存储器件和方法，例如涉及包括包含轻掺杂多晶硅的浮动栅极的存储单元的那些，其中轻掺杂多晶硅具有基本均匀的掺杂浓度。一个这样的存储单元还包括设置在浮置栅极和控制栅极之间的控制栅极和电介质。

8. 发明授权

US07277328B2 Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices 有权
标题翻译：用于中和浮栅存储器单元和器件的隧道氧化物中隧道氧化物中的空穴的方法
公开(公告)号：US07277328B2
公开(公告)日：2007-10-02
申请号：US11217828
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.
摘要翻译：使用第一极性的源极电压的幅度的减小来中和浮栅存储器单元的隧道氧化物中的空穴的方法，以增加第二极性的控制栅极电压的幅度。

9. 发明授权

US07277327B2 Methods for erasing flash memory 有权
公开(公告)号：US07277327B2
公开(公告)日：2007-10-02
申请号：US11216956
申请日：2005-08-31
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

10. 发明授权

US07257024B2 Minimizing adjacent wordline disturb in a memory device 有权
公开(公告)号：US07257024B2
公开(公告)日：2007-08-14
申请号：US11417575
申请日：2006-05-04
申请人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
发明人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

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