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71. 发明申请

US20090212272A1 SELF-CONVERGING BOTTOM ELECTRODE RING 失效
标题翻译：自适应底部电极环
公开(公告)号：US20090212272A1
公开(公告)日：2009-08-27
申请号：US12036372
申请日：2008-02-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
IPC分类号： H01L21/06 , H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683 , Y10S438/90
摘要： A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.
摘要翻译：一种包括自会聚底电极环的方法和存储单元。该方法包括在衬底上形成台阶间隔物，顶部绝缘层，中间绝缘层和底部绝缘层。该方法包括在顶部绝缘层和中间绝缘层内形成台阶间隔物。台阶垫片尺寸易于控制。该方法还包括在步骤间隔物作为掩模的底部绝缘层中形成通道。所述方法包括在所述通道内形成底部电极环，所述通道包括所述通道内的杯形外部导电层，并且在所述杯形外部导电层内形成内部绝缘层。该方法包括在底部电极环上方形成相变层和在底部电极环上方形成顶部电极。

72. 发明授权

US07563639B2 Phase-changeable memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07563639B2
公开(公告)日：2009-07-21
申请号：US11733131
申请日：2007-04-09
申请人： Hee-Ju Shin , Jong-Chan Shin , Soon-Oh Park , Hyeong-Geun An , Han-Bong Ko
发明人： Hee-Ju Shin , Jong-Chan Shin , Soon-Oh Park , Hyeong-Geun An , Han-Bong Ko
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.
摘要翻译：在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。第一插头形成在第一开口中。将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。包括相变材料的第二插头形成在第二开口中。导线和上电极分别形成在第一插头和第二插头上。

73. 发明申请

US20090154227A1 INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS 有权
标题翻译：集成电路，包括二极管记忆体
公开(公告)号：US20090154227A1
公开(公告)日：2009-06-18
申请号：US11957964
申请日：2007-12-17
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/003 , G11C11/36 , G11C13/0004 , G11C13/0023 , G11C2213/71 , G11C2213/72 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
摘要翻译：集成电路包括晶体管和耦合到晶体管的触点。集成电路包括耦合到触点的第一二极管电阻率变化材料存储单元和耦合到触点的第二二极管电阻率变化材料存储单元。第二二极管电阻率变化材料存储单元位于第一二极管电阻率变化材料存储单元上方。

74. 发明授权

US07547569B2 Method for patterning Mo layer in a photovoltaic device comprising CIGS material using an etch process 失效
标题翻译：使用蚀刻工艺在包括CIGS材料的光伏器件中图案化Mo层的方法
公开(公告)号：US07547569B2
公开(公告)日：2009-06-16
申请号：US11562573
申请日：2006-11-22
申请人： Timothy Weidman , Li Xu , Peter G. Borden
发明人： Timothy Weidman , Li Xu , Peter G. Borden
IPC分类号： H01L21/00 , H01L21/06
CPC分类号： H01L31/0749 , H01L31/03923 , H01L31/0465 , H01L31/18 , Y02E10/541
摘要： A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.
摘要翻译：本文所述的处理方法提供了一种图案化MoSe 2和/或Mo材料的方法，例如薄膜结构中的这种材料层。根据一个方面，本发明涉及可以有效地通过Mo和/或MoSe2蚀刻的蚀刻溶液。根据另一方面，本发明涉及当这种材料在薄膜光伏器件中用其它材料加工时蚀刻这种材料。根据其它方面，本发明包括在整个工艺流程中对具有选择性的CIGS材料的Mo和/或MoSe2进行蚀刻的工艺。根据另外的方面，本发明涉及可用于在光伏器件中形成光伏电池和/或互连和测试结构的整体光刻工艺中的Mo和/或MoSe2蚀刻溶液。

75. 发明申请

US20090121211A1 Solution-Based Deposition Process for Metal Chalcogenides 有权
标题翻译：金属硫族化合物的溶液沉积工艺
公开(公告)号：US20090121211A1
公开(公告)日：2009-05-14
申请号：US12355189
申请日：2009-01-16
申请人： David B. Mitzi , Simone Raoux
发明人： David B. Mitzi , Simone Raoux
IPC分类号： H01L45/00 , H01L21/06 , H01L29/18
CPC分类号： H01L29/1029 , C01B21/16 , C23C18/04 , C23C18/1204 , C23C18/1275 , H01L29/78681 , Y10T428/31504
摘要： A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices.
摘要翻译：通过向肼化合物中加入元素金属和元素硫族元素，制备金属硫属元素化合物的肼基前体溶液。前体溶液可用于形成膜。前体溶液可用于制备场效应晶体管，光伏器件和相变存储器件。

76. 发明申请

US20090114897A1 PHASE CHANGE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：能够增加感测尺寸的相变记忆装置及其制造方法
公开(公告)号：US20090114897A1
公开(公告)日：2009-05-07
申请号：US12045280
申请日：2008-03-10
申请人： Heon Yong CHANG
发明人： Heon Yong CHANG
IPC分类号： H01L29/02 , H01L21/06
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233
摘要： A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes.
摘要翻译：一种能够增加感测裕度的相变存储器件及其制造方法。相变存储器件包括形成有限定有源区的器件隔离结构的半导体衬底; 形成在活性区域的表面上并具有直线形状的第一导电型杂质区; 第二导电类型阱，其在比器件隔离结构低的位置形成在半导体衬底中; 在半导体衬底中形成在器件隔离结构的下端与半导体衬底之间的边界处的第二导电型离子注入层; 形成在第一导电型杂质区上的多个垂直PN二极管; 以及形成在垂直PN二极管上的相变存储单元。

77. 发明申请

US20090072211A1 Resistive random access memory and method for manufacturing the same 有权
标题翻译：电阻随机存取存储器及其制造方法
公开(公告)号：US20090072211A1
公开(公告)日：2009-03-19
申请号：US11898529
申请日：2007-09-13
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1633
摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.
摘要翻译：提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。绝缘层设置在底部电极上。绝缘层具有第一宽度的接触孔。硬掩模层具有开口。存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。顶部电极设置在绝缘层上并与存储单元耦合。

78. 发明授权

US07473576B2 Method for making a self-converged void and bottom electrode for memory cell 有权
标题翻译：制造用于存储单元的自会聚空隙和底部电极的方法
公开(公告)号：US07473576B2
公开(公告)日：2009-01-06
申请号：US11567326
申请日：2006-12-06
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L21/06
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.
摘要翻译：形成包括导电元件的基层。在基层上形成包括第三下平面化停止层，第二层和第一上层的上层。键孔通过上层形成，露出基层中导电元件的表面。第一层具有延伸到开口中的突出部分，使得第一层中的开口比第二层中的开口短。电介质材料沉积到锁眼孔中以在沉积的介电材料内形成自会聚空隙。在一些示例中，键孔形成步骤包括增加第一层的体积，而在其他示例中，键孔形成步骤包括蚀刻第二层。

79. 发明申请

US20090001337A1 Phase Change Memory Cell with Vertical Transistor 有权
标题翻译：具有垂直晶体管的相变存储单元
公开(公告)号：US20090001337A1
公开(公告)日：2009-01-01
申请号：US11771457
申请日：2007-06-29
申请人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L21/336 , H01L21/06 , H01L29/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1683
摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.
摘要翻译：部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。岛形成在下电极特征上并具有一个或多个侧壁。它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

80. 发明申请

US20080299701A1 Front-end processing of nickel plated bond pads 有权
标题翻译：镀镍接合垫的前端加工
公开(公告)号：US20080299701A1
公开(公告)日：2008-12-04
申请号：US12219836
申请日：2008-07-29
申请人： John Moore , Joseph F. Brooks
发明人： John Moore , Joseph F. Brooks
IPC分类号： H01L21/06
CPC分类号： H01L24/06 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/53257 , H01L24/03 , H01L24/05 , H01L27/24 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/1608 , H01L45/1675 , H01L2224/0311 , H01L2224/05014 , H01L2224/05147 , H01L2224/0555 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/06179 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/05042 , H01L2924/14 , H01L2924/1443 , H01L2924/19041 , H01L2924/2064 , H01L2924/00014
摘要： A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
摘要翻译：一种在存储器件中使用的铜接合焊盘上制造镀镍帽的前端方法。该方法提供了保护接合焊盘免受氧化气氛的影响，而不会在制造期间将存储器件中的敏感结构暴露于铜。

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