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71. 发明授权

US5287386A Differential driver/receiver circuit 失效
标题翻译：差分驱动器/接收器电路
公开(公告)号：US5287386A
公开(公告)日：1994-02-15
申请号：US676132
申请日：1991-03-27
申请人： Jon P. Wade , David S. Wells
发明人： Jon P. Wade , David S. Wells
IPC分类号： H03K3/356 , H03K5/02 , H03K17/16 , H03K17/687 , H03K17/693 , H03K19/003 , H04B3/50 , H04L25/02 , H04L25/03 , H04B3/00
CPC分类号： H04L25/028 , H03K17/164 , H03K17/693 , H03K3/356147 , H03K5/023 , H04L25/0272 , H04L25/0292 , H04L25/03834
摘要： A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal. The receiver circuit, during normal receiving operations, generates true and complement signals in response to the differential receive signal pair. During a test mode, the receiver circuit, in separate steps, compares the voltage levels of the true and complement receive signals to threshold voltages and generates an error signal if the selected true or complement receive signal does not have the proper relationship to the voltage level of the threshold voltage.
摘要翻译：一种用于发送和接收差分信号对的新的驱动器电路和接收器电路。驱动器电路包括串联产生差分信号对的真和补码信号产生元件。每个真实和补码信号产生元件包括高增益元件和至少一个低增益元件。延迟电路响应于真实和补码数据信号，用于迭代地控制每个信号产生元件的高增益元件和低增益元件以产生差分信号对，延迟电路控制高增益元件相对于低增益元件的延迟，从而减少差分信号对中的振铃。接收器电路接收差分接收信号对，其包括在一对输入线上具有选定条件的真和补码接收信号，并产生真实和补码数据信号。在正常接收操作期间，接收机电路响应于差分接收信号对而产生真实和补码信号。在测试模式期间，接收器电路在单独的步骤中，将真实和补码接收信号的电压电平与阈值电压进行比较，并且如果所选择的真或接收信号与电压电平没有正确关系，则产生误差信号的阈值电压。

72. 发明授权

US5265124A Integrated multi-port repeater having shared resources 失效
标题翻译：具有共享资源的集成多端口中继器
公开(公告)号：US5265124A
公开(公告)日：1993-11-23
申请号：US595061
申请日：1990-10-10
申请人： David Staab , Nader Vijeh
发明人： David Staab , Nader Vijeh
IPC分类号： H04B3/36 , G01R29/027 , H03K5/02 , H03K5/156 , H03K5/26 , H03K19/0185 , H04L12/28 , H04L12/44 , H04L12/46 , H04L25/02 , H04L25/08 , H04L25/49
CPC分类号： H04L12/44 , G01R29/0273 , H03K19/018578 , H03K5/023 , H03K5/156 , H04L12/46 , H04L25/08 , H04L25/085 , H04L25/4904 , H04L25/0272
摘要： A discrete integrated repeater device and port MAU/AUI functions shares resources among its several ports. The device includes a single multi-bit free running counter providing preselected timing intervals to a plurality of latches. A signal undergoing measurement clears the latch while a preselected timing signal sets the latch. Receipt of a timing signal at a set latch indicates success or failure of some particular condition under test. The device satisfies an IEEE 802.3 specification for execution of a link integrity test. The device is also able to selectively disable or enable the link integrity test function for particular ports. A plurality of latches, one associated with each port, is set upon carrier sense detection at the particular port. A token passing mechanism implemented with a daisy chained line coupled to each latch enables a polling of each latch to provide carrier sense information about each port in a serial format. The device shares a single PLL among all its ports by producing a logical sum of carrier sense inputs to enable activation of the PLL. A collision indication signal will override operation of the PLL to ensure data integrity and to allow the PLL to reacquire lock on its reference clock.
摘要翻译：一个离散集成中继器设备和端口MAU / AUI功能在其多个端口之间共享资源。该设备包括单个多位自由运行计数器，为多个锁存器提供预选的定时间隔。正在进行测量的信号会在预选的定时信号设置锁存器时清除锁存器。在设置的锁存器处接收定时信号指示被测试的一些特定条件的成功或失败。该设备满足用于执行链路完整性测试的IEEE 802.3规范。该设备还能够选择性地禁用或启用特定端口的链路完整性测试功能。多个锁存器，一个与每个端口相关联的锁存器被设置在特定端口的载波检测检测。通过耦合到每个锁存器的菊花链链路实现的令牌传递机制使得能够轮询每个锁存器以串行格式提供关于每个端口的载波感测信息。该器件通过产生载波检测输入的逻辑和来实现PLL的激活，在其所有端口中共享单个PLL。冲突指示信号将覆盖PLL的操作，以确保数据完整性，并允许PLL重新获取其参考时钟上的锁定。

73. 发明授权

US5265123A Expandable repeater 失效
标题翻译：可扩展中继器
公开(公告)号：US5265123A
公开(公告)日：1993-11-23
申请号：US556046
申请日：1990-07-20
申请人： Nader Vijeh , David Staab
发明人： Nader Vijeh , David Staab
IPC分类号： H04B3/36 , H03K5/02 , H03K5/156 , H03K19/0185 , H04L12/44 , H04L25/02 , H04L25/08 , H04L25/49 , H04B3/16
CPC分类号： H03K5/023 , H03K19/018578 , H03K5/156 , H04L12/44 , H04L25/08 , H04L25/085 , H04L25/4904 , H04L25/0272
摘要： A discrete repeater having a predetermined number of ports includes an expansion port permitting connection of one or more of similar devices to produce a single repeater unit having an increased number of ports. The expansion port includes two bidirectional channels, an output channel and two input channels. An arbiter function connects to each discrete repeater to assert appropriate signals to permit the discrete repeaters making up a repeater unit to exchange data and collision information. This exchange of data is used in a state machine of the discrete repeaters to provide a repeater unit with distributed repeater and relay functions.
摘要翻译：具有预定数量的端口的离散中继器包括允许一个或多个类似设备连接以产生具有增加端口数量的单个中继器单元的扩展端口。扩展端口包括两个双向通道，一个输出通道和两个输入通道。仲裁器功能连接到每个离散中继器以断言适当的信号，以允许构成中继器单元的离散中继器交换数据和冲突信息。这种数据交换在离散中继器的状态机中使用，以提供具有分布式中继器和中继功能的中继器单元。

74. 发明授权

US5257287A Automatic polarity detection and correction method and apparatus employing linkpulses 失效
标题翻译：采用连续脉冲的自动极性检测和校正方法及装置
公开(公告)号：US5257287A
公开(公告)日：1993-10-26
申请号：US620980
申请日：1990-11-30
申请人： Jeffrey M. Blumenthal , Nader Vijeh , John M. Wincn , Ian S. Crayford
发明人： Jeffrey M. Blumenthal , Nader Vijeh , John M. Wincn , Ian S. Crayford
IPC分类号： H03M7/00 , H03K5/02 , H03K5/13 , H03K5/1534 , H03K5/156 , H03K19/0185 , H03M5/12 , H04L25/02 , H04L25/08 , H04L25/49 , H04L25/34
CPC分类号： H03K5/023 , H03K19/018578 , H03K5/13 , H03K5/1534 , H03K5/156 , H04L25/02 , H04L25/0272 , H04L25/0292 , H04L25/08 , H04L25/085 , H04L25/4904
摘要： A differential receiver incorporated into a MAU which receives both Manchester packets and linkpulses according to the IEEE 802.3 10Base-T standard has polarity detection and correction circuit for automatically detecting a reversed polarity for RD input lines. The differential receiver samples incoming pulses for time, amplitude and pulse width qualification and makes a preliminary polarity determination based upon polarity of such qualified pulses. This preliminary polarity allows a linktest state machine to transition to a link.sub.-- pass state, enabling output drivers of the MAU. Additionally, the linkpulse polarity information initially makes a polarity determination for the entire differential receiver which asserts a FIX POLARITY signal. The FIX POLARITY signal controls a correction circuit which internally remedies reversed input lines. Preferably, the correction circuit internally reroutes the signals. An ETD polarity circuit makes polarity determinations from any ETD information received, as effected by the correction circuit. The ETD polarity circuit independently controls the linkpulse polarity determinations and conflicting determinations are resolved in favor of the ETD polarity circuit. Upon detecting two consecutive, consistent valid ETDs, the ETD polarity circuit locks-in the polarity determinations until a reset or a linkfail condition. The correction circuit effects both Manchester packets and linkpulses, so an incorrectly locked polarity will produce inverted linkpulses which will not allow the MAU to remain in the link.sub.-- pass state. In the linkfail state, the MAU may reestablish the correct polarity.
摘要翻译：根据IEEE 802.3 10Base-T标准，并入到接收曼彻斯特分组和链路脉冲的MAU中的差分接收机具有用于自动检测RD输入线的反极性的极性检测和校正电路。差分接收器对输入脉冲进行时间，幅度和脉冲宽度鉴定，并根据这种合格脉冲的极性进行初步极性判定。该初步极性允许链路测试状态机转换到链路通过状态，使得MAU的输出驱动器成为可能。此外，链路脉冲极性信息最初对整个差分接收机进行极性确定，这个确定了FIX POLARITY信号。 FIX POLARITY信号控制一个校正电路，内部补救反向输入线路。优选地，校正电路在内部重新路由信号。 ETD极性电路根据校正电路实现的任何接收的ETD信息进行极性判定。 ETD极性电路独立控制链路脉冲极性判定，冲突确定有利于ETD极性电路。在检测到两个连续的，一致的有效ETD时，ETD极性电路锁定极性确定，直到复位或链接状态。校正电路影响曼彻斯特数据包和链路脉冲，因此锁定不正确的极性将产生反向的链路脉冲，这将不允许MAU保持链路通过状态。在链接状态下，MAU可能会重新建立正确的极性。

75. 发明授权

US4617479B1 PROGRAMMABLE LOGIC ARRAY DEVICE USING EPROM TECHNOLOGY 失效
标题翻译：可编程逻辑阵列设备使用EPROM技术
公开(公告)号：US4617479B1
公开(公告)日：1993-09-21
申请号：US60701884
申请日：1984-05-03
申请人： ALTERA SEMICONDUCTOR CORP.
发明人： ROBERT F. HARTMANN , SAU-CHING WONG , YIU-FAI CHAN , JUNG-HSING OU
IPC分类号： H03K5/02 , H03K19/094 , H03K19/177 , G06F7/00 , H03K19/20
CPC分类号： H03K19/17712 , H03K5/023 , H03K19/09425

76. 发明授权

US5237527A Pulse shaping filter 失效
标题翻译：脉冲形状滤波器
公开(公告)号：US5237527A
公开(公告)日：1993-08-17
申请号：US798811
申请日：1991-11-27
申请人： Minoru Oda
发明人： Minoru Oda
IPC分类号： H03H11/04 , H03H11/12 , H03K5/02
CPC分类号： H03K5/02
摘要： A pulse shaping filter for use in pulse height analysis, wherein a plurality of semi-gaussian filters of different time constants are provided, which generate a plurality of signals of semi-gaussian shape with different pulse widths from one input signal, and added the plurality of signals after delaying them in a manner that the signal of the semi-gaussian filter of the smaller time constant is delayed longer, thereby to obtain a signal of approximately cusp shaping.
摘要翻译：一种用于脉冲高度分析的脉冲整形滤波器，其中提供了不同时间常数的多个半高斯滤波器，其产生具有来自一个输入信号的不同脉冲宽度的多个具有不同脉冲宽度的半高斯形状的信号，并将多个的信号，以使得较小时间常数的半高斯滤波器的信号被延迟更长的方式延迟它们，从而获得近似尖点整形的信号。

77. 发明授权

US5220587A Output circuit for a CCD with a D.C. restoration circuit integrated together with the CCD in a monolithic semiconductor chip 失效
标题翻译：具有D.C.恢复电路的CCD与CCD在单片半导体芯片中集成的输出电路
公开(公告)号：US5220587A
公开(公告)日：1993-06-15
申请号：US799142
申请日：1991-11-27
申请人： Iwao Takemoto , Tatsuhisa Fujii , Atsushi Hasegawa
发明人： Iwao Takemoto , Tatsuhisa Fujii , Atsushi Hasegawa
IPC分类号： H01L27/148 , H01L21/339 , H01L29/762 , H03F3/193 , H03K5/02 , H03K19/0944
CPC分类号： H04N5/361 , H03F3/193 , H03K5/026 , H04N5/3575 , H04N5/372 , H04N5/378
摘要： An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.
摘要翻译：源极接地形式的放大MOSFET通过第二个电容器在其栅极接收源极跟随器电路的输出信号。另一方面，源跟随器电路接收接收信号电荷的第一电容器的电压。当第一电容器的信号电荷被复位时，通过开关装置将预定的偏置电压提供给放大MOSFET的栅极。根据该结构，第二电容器只能传输信号分量，电压信号本身可以由源极接地型放大MOSFET放大。在第一电容器的复位期间，放大MOSFET可以被开关器件偏置到其最佳工作点; 因此，通过简单的电路结构可以显着提高灵敏度。

78. 发明授权

US5214330A Bi-directional signal buffering circuit 失效
标题翻译：双向信号缓冲电路
公开(公告)号：US5214330A
公开(公告)日：1993-05-25
申请号：US855530
申请日：1992-03-20
申请人： Yoshihiko Okazaki
发明人： Yoshihiko Okazaki
IPC分类号： G06F13/38 , G06F13/40 , H03K5/02
CPC分类号： H03K5/023
摘要： When a signal A is input to a bi-directional buffer from a bus A, a first buffer detects the level of the signal A and supplies an OE control signal to a second buffer to disable an output therefrom. The output from the second buffer is set to a predetermined value by a bias circuit, and this predetermined value is supplied to the bi-directional buffer as a direction control signal via a direction designator together with output signal from the first buffer. In this circuit operation, when the signal A is input to the bi-directional buffer, it is immediately transmitted from the bus A side to the bus B side since the bi-directional buffer is set in an initial state by the bias circuit so as to transmit a signal in two directions.
摘要翻译：当信号A从总线A输入到双向缓冲器时，第一缓冲器检测信号A的电平，并将OE控制信号提供给第二缓冲器以禁用其输出。通过偏置电路将来自第二缓冲器的输出设置为预定值，并且该预定值与来自第一缓冲器的输出信号一起经由方向指示器作为方向控制信号提供给双向缓冲器。在该电路操作中，当信号A被输入到双向缓冲器时，它立即从总线A侧发送到总线B侧，因为双向缓冲器被偏置电路设置在初始状态，以便以在两个方向上发送信号。

79. 发明授权

US5151680A Speaker driver 失效
标题翻译：扬声器驱动器
公开(公告)号：US5151680A
公开(公告)日：1992-09-29
申请号：US692771
申请日：1991-04-26
申请人： Koji Yamasaki
发明人： Koji Yamasaki
IPC分类号： H04Q7/14 , G08B3/10 , H03G3/00 , H03K5/02 , H04B1/16 , H04Q7/06 , H04R3/00
CPC分类号： G08B3/10
摘要： A speaker driver is operated by a battery and drives a speaker to generate an alert tone in response to an externally input intermittent signal. The speaker driver includes a reference voltage generator for generating a reference voltage, a transconductance amplifier for outputting a current corresponding to a differential voltage between a voltage of the battery and the reference voltage, an output control switch for ON/OFF-controlling the output current from the transconductance amplifier in accordance with the intermittent signal, and a DC amplifier for amplifying the ON/OFF-controlled output current as a driving current for the speaker. Since a speaker driving current is decreased as a power source voltage is dropped, an abnormal voltage drop during an alert generation period can be prevented, thereby prolonging the service life of a battery.

80. 发明授权

US5120991A Driver circuit for converting a CMOS level signal to a high-voltage level 失效
标题翻译：将CMOS电平信号转换为高电平电平的驱动电路
公开(公告)号：US5120991A
公开(公告)日：1992-06-09
申请号：US457771
申请日：1990-01-12
申请人： Nobuyuki Takahashi
发明人： Nobuyuki Takahashi
IPC分类号： G06F3/00 , H03K5/02 , H03K17/04 , H03K17/0412 , H03K17/567 , H03K17/687 , H03K19/0175
CPC分类号： H03K17/567 , H03K17/0406 , H03K17/04123
摘要： There is disclosed a driver circuit for driving a flat panel display. In this invention, a gate bias for a MOS transistor for charging an output terminal to high level is generated by a constant voltage element. The value of a current supplied to the constant voltage element is controlled by a current control circuit. In order to turn off the charging MOS transistor, a MOS transistor for discharging the node of the gate of the charging MOS transistor is set in an ON state. In order to switch an output, two drive signals are output from a drive signal generator to turn off both the charging MOS transistor for charging the output terminal to high level and the discharging MOS transistor for discharging the output terminal to low level.

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